projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 896e2ca9 LW |
1 | /* |
| 2 | * (C) Copyright 2011 | |
| 3 | * Marvell Semiconductor <www.marvell.com> | |
| 4 | * Written-by: Lei Wen <leiwen@marvell.com> | |
| 5 | * | |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
| 22 | * MA 02110-1301 USA | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef _PANTHEON_CPU_H | |
| 26 | #define _PANTHEON_CPU_H | |
| 27 | ||
| 28 | #include <asm/io.h> | |
| 29 | #include <asm/system.h> | |
| 30 | ||
| 31 | /* | |
| 32 | * Main Power Management (MPMU) Registers | |
| 33 | * Refer Register Datasheet 9.1 | |
| 34 | */ | |
| 35 | struct panthmpmu_registers { | |
| 36 | u8 pad0[0x0024]; | |
| 37 | u32 ccgr; /*0x0024*/ | |
| 38 | u8 pad1[0x0200 - 0x024 - 4]; | |
| 39 | u32 wdtpcr; /*0x0200*/ | |
| 40 | u8 pad2[0x1020 - 0x200 - 4]; | |
| 41 | u32 aprr; /*0x1020*/ | |
| 42 | u32 acgr; /*0x1024*/ | |
| 43 | }; | |
| 44 | ||
| 45 | /* | |
| 46 | * APB Clock Reset/Control Registers | |
| 47 | * Refer Register Datasheet 6.14 | |
| 48 | */ | |
| 49 | struct panthapb_registers { | |
| 50 | u32 uart0; /*0x000*/ | |
| 51 | u32 uart1; /*0x004*/ | |
| 52 | u32 gpio; /*0x008*/ | |
| aa3b168e LW |
53 | u8 pad0[0x02c - 0x08 - 4]; |
| 54 | u32 twsi; /*0x02c*/ | |
| 55 | u8 pad1[0x034 - 0x2c - 4]; | |
| 896e2ca9 LW |
56 | u32 timers; /*0x034*/ |
| 57 | }; | |
| 58 | ||
| 59 | /* | |
| 60 | * CPU Interface Registers | |
| 61 | * Refer Register Datasheet 4.3 | |
| 62 | */ | |
| 63 | struct panthcpu_registers { | |
| 64 | u32 chip_id; /* Chip Id Reg */ | |
| 65 | u32 pad; | |
| 66 | u32 cpu_conf; /* CPU Conf Reg */ | |
| 67 | u32 pad1; | |
| 68 | u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ | |
| 69 | u32 pad2; | |
| 70 | u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ | |
| 71 | u32 mcb_conf; /* MCB Conf Reg */ | |
| 72 | u32 sys_boot_ctl; /* Sytem Boot Control */ | |
| 73 | }; | |
| 74 | ||
| 75 | /* | |
| 76 | * Functions | |
| 77 | */ | |
| 78 | u32 panth_sdram_base(int); | |
| 79 | u32 panth_sdram_size(int); | |
| 80 | ||
| 81 | #endif /* _PANTHEON_CPU_H */ |