]> git.ipfire.org Git - people/ms/u-boot.git/blame - arch/arm/include/asm/arch-rockchip/boot0.h
rockchip: boot0 hook: support early return for RK3188/RK3066-style BROM
[people/ms/u-boot.git] / arch / arm / include / asm / arch-rockchip / boot0.h
CommitLineData
3d54eabc
PT
1/*
2 * Copyright 2017 Theobroma Systems Design und Consulting GmbH
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * Execution starts on the instruction following this 4-byte header
cee7470c
KY
9 * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33'). This
10 * magic constant will be written into the final image by the rkimage
11 * tool, but we need to reserve space for it here.
3d54eabc
PT
12 *
13 * To make life easier for everyone, we build the SPL binary with
14 * space for this 4-byte header already included in the binary.
15 */
3d54eabc 16#ifdef CONFIG_SPL_BUILD
700f3108
PT
17 /*
18 * We need to add 4 bytes of space for the 'RK33' at the
19 * beginning of the executable. However, as we want to keep
20 * this generic and make it applicable to builds that are like
21 * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
b377d222
PT
22 * TPL, but extra space needed in the SPL), we simply insert
23 * a branch-to-next-instruction-word with the expectation that
24 * the first one may be overwritten, if this is the first stage
25 * contained in the final image created with mkimage)...
700f3108 26 */
b377d222
PT
27 b 1f /* if overwritten, entry-address is at the next word */
281:
29#endif
30#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
31 adr r3, entry_counter
32 ldr r0, [r3]
33 cmp r0, #1 /* check if entry_counter == 1 */
34 beq reset /* regular bootup */
35 add r0, #1
36 str r0, [r3] /* increment the entry_counter in memory */
37 mov r0, #0 /* return 0 to the BROM to signal 'OK' */
38 bx lr /* return control to the BROM */
39entry_counter:
40 .word 0
3d54eabc
PT
41#endif
42 b reset
cee7470c
KY
43#if !defined(CONFIG_ARM64)
44 /*
45 * For armv7, the addr '_start' will used as vector start address
46 * and write to VBAR register, which needs to aligned to 0x20.
47 */
b377d222 48 .align(5), 0x0
cee7470c
KY
49_start:
50 ARM_VECTORS
51#endif
fa1392a2
KY
52
53#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
54 .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
55#endif