[people/ms/u-boot.git] / arch / arm / include / asm / arch-rockchip / grf_rk3328.h

/*
 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
#define __SOC_ROCKCHIP_RK3328_GRF_H__

struct rk3328_grf_regs {
	u32 gpio0a_iomux;
	u32 gpio0b_iomux;
	u32 gpio0c_iomux;
	u32 gpio0d_iomux;
	u32 gpio1a_iomux;
	u32 gpio1b_iomux;
	u32 gpio1c_iomux;
	u32 gpio1d_iomux;
	u32 gpio2a_iomux;
	u32 gpio2bl_iomux;
	u32 gpio2bh_iomux;
	u32 gpio2cl_iomux;
	u32 gpio2ch_iomux;
	u32 gpio2d_iomux;
	u32 gpio3al_iomux;
	u32 gpio3ah_iomux;
	u32 gpio3bl_iomux;
	u32 gpio3bh_iomux;
	u32 gpio3c_iomux;
	u32 gpio3d_iomux;
	u32 com_iomux;
	u32 reserved1[(0x100 - 0x54) / 4];

	u32 gpio0a_p;
	u32 gpio0b_p;
	u32 gpio0c_p;
	u32 gpio0d_p;
	u32 gpio1a_p;
	u32 gpio1b_p;
	u32 gpio1c_p;
	u32 gpio1d_p;
	u32 gpio2a_p;
	u32 gpio2b_p;
	u32 gpio2c_p;
	u32 gpio2d_p;
	u32 gpio3a_p;
	u32 gpio3b_p;
	u32 gpio3c_p;
	u32 gpio3d_p;
	u32 reserved2[(0x200 - 0x140) / 4];
	u32 gpio0a_e;
	u32 gpio0b_e;
	u32 gpio0c_e;
	u32 gpio0d_e;
	u32 gpio1a_e;
	u32 gpio1b_e;
	u32 gpio1c_e;
	u32 gpio1d_e;
	u32 gpio2a_e;
	u32 gpio2b_e;
	u32 gpio2c_e;
	u32 gpio2d_e;
	u32 gpio3a_e;
	u32 gpio3b_e;
	u32 gpio3c_e;
	u32 gpio3d_e;
	u32 reserved3[(0x300 - 0x240) / 4];
	u32 gpio0l_sr;
	u32 gpio0h_sr;
	u32 gpio1l_sr;
	u32 gpio1h_sr;
	u32 gpio2l_sr;
	u32 gpio2h_sr;
	u32 gpio3l_sr;
	u32 gpio3h_sr;
	u32 reserved4[(0x380 - 0x320) / 4];
	u32 gpio0l_smt;
	u32 gpio0h_smt;
	u32 gpio1l_smt;
	u32 gpio1h_smt;
	u32 gpio2l_smt;
	u32 gpio2h_smt;
	u32 gpio3l_smt;
	u32 gpio3h_smt;
	u32 reserved5[(0x400 - 0x3a0) / 4];
	u32 soc_con[11];
	u32 reserved6[(0x480 - 0x42c) / 4];
	u32 soc_status[5];
	u32 reserved7[(0x4c0 - 0x494) / 4];
	u32 otg3_con[2];
	u32 reserved8[(0x500 - 0x4c8) / 4];
	u32 cpu_con[2];
	u32 reserved9[(0x520 - 0x508) / 4];
	u32 cpu_status[2];
	u32 reserved10[(0x5c8 - 0x528) / 4];
	u32 os_reg[8];
	u32 reserved11[(0x680 - 0x5e8) / 4];
	u32 sig_detect_con;
	u32 reserved12[3];
	u32 sig_detect_status;
	u32 reserved13[3];
	u32 sig_detect_status_clr;
	u32 reserved14[3];

	u32 sdmmc_det_counter;
	u32 reserved15[(0x700 - 0x6b4) / 4];
	u32 host0_con[3];
	u32 reserved16[(0x880 - 0x70c) / 4];
	u32 otg_con0;
	u32 reserved17[3];
	u32 host0_status;
	u32 reserved18[(0x900 - 0x894) / 4];
	u32 mac_con[3];
	u32 reserved19[(0xb00 - 0x90c) / 4];
	u32 macphy_con[4];
	u32 macphy_status;
};
check_member(rk3328_grf_regs, macphy_status, 0xb10);

struct rk3328_sgrf_regs {
	u32 soc_con[6];
	u32 reserved0[(0x100 - 0x18) / 4];
	u32 dmac_con[6];
	u32 reserved1[(0x180 - 0x118) / 4];
	u32 fast_boot_addr;
	u32 reserved2[(0x200 - 0x184) / 4];
	u32 chip_fuse_con;
	u32 reserved3[(0x280 - 0x204) / 4];
	u32 hdcp_key_reg[8];
	u32 hdcp_key_access_mask;
};
check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);


#endif	/* __SOC_ROCKCHIP_RK3328_GRF_H__ */
Commit	Line	Data
d439a46e KY	1	/*
	2	* (C) Copyright 2016 Rockchip Electronics Co., Ltd
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
	8	#define __SOC_ROCKCHIP_RK3328_GRF_H__
	9
	10	struct rk3328_grf_regs {
	11	u32 gpio0a_iomux;
	12	u32 gpio0b_iomux;
	13	u32 gpio0c_iomux;
	14	u32 gpio0d_iomux;
	15	u32 gpio1a_iomux;
	16	u32 gpio1b_iomux;
	17	u32 gpio1c_iomux;
	18	u32 gpio1d_iomux;
	19	u32 gpio2a_iomux;
	20	u32 gpio2bl_iomux;
	21	u32 gpio2bh_iomux;
	22	u32 gpio2cl_iomux;
	23	u32 gpio2ch_iomux;
	24	u32 gpio2d_iomux;
	25	u32 gpio3al_iomux;
	26	u32 gpio3ah_iomux;
	27	u32 gpio3bl_iomux;
	28	u32 gpio3bh_iomux;
	29	u32 gpio3c_iomux;
	30	u32 gpio3d_iomux;
	31	u32 com_iomux;
	32	u32 reserved1[(0x100 - 0x54) / 4];
	33
	34	u32 gpio0a_p;
	35	u32 gpio0b_p;
	36	u32 gpio0c_p;
	37	u32 gpio0d_p;
	38	u32 gpio1a_p;
	39	u32 gpio1b_p;
	40	u32 gpio1c_p;
	41	u32 gpio1d_p;
	42	u32 gpio2a_p;
	43	u32 gpio2b_p;
	44	u32 gpio2c_p;
	45	u32 gpio2d_p;
	46	u32 gpio3a_p;
	47	u32 gpio3b_p;
	48	u32 gpio3c_p;
	49	u32 gpio3d_p;
	50	u32 reserved2[(0x200 - 0x140) / 4];
	51	u32 gpio0a_e;
	52	u32 gpio0b_e;
	53	u32 gpio0c_e;
	54	u32 gpio0d_e;
	55	u32 gpio1a_e;
	56	u32 gpio1b_e;
	57	u32 gpio1c_e;
	58	u32 gpio1d_e;
	59	u32 gpio2a_e;
	60	u32 gpio2b_e;
	61	u32 gpio2c_e;
	62	u32 gpio2d_e;
	63	u32 gpio3a_e;
	64	u32 gpio3b_e;
65	u32 gpio3c_e;
66	u32 gpio3d_e;
67	u32 reserved3[(0x300 - 0x240) / 4];
68	u32 gpio0l_sr;
69	u32 gpio0h_sr;
70	u32 gpio1l_sr;
71	u32 gpio1h_sr;
72	u32 gpio2l_sr;
73	u32 gpio2h_sr;
74	u32 gpio3l_sr;
75	u32 gpio3h_sr;
76	u32 reserved4[(0x380 - 0x320) / 4];
77	u32 gpio0l_smt;
78	u32 gpio0h_smt;
79	u32 gpio1l_smt;
80	u32 gpio1h_smt;
81	u32 gpio2l_smt;
82	u32 gpio2h_smt;
83	u32 gpio3l_smt;
84	u32 gpio3h_smt;
85	u32 reserved5[(0x400 - 0x3a0) / 4];
86	u32 soc_con[11];
87	u32 reserved6[(0x480 - 0x42c) / 4];
88	u32 soc_status[5];
89	u32 reserved7[(0x4c0 - 0x494) / 4];
90	u32 otg3_con[2];
91	u32 reserved8[(0x500 - 0x4c8) / 4];
92	u32 cpu_con[2];
93	u32 reserved9[(0x520 - 0x508) / 4];
94	u32 cpu_status[2];
95	u32 reserved10[(0x5c8 - 0x528) / 4];
96	u32 os_reg[8];
97	u32 reserved11[(0x680 - 0x5e8) / 4];
98	u32 sig_detect_con;
99	u32 reserved12[3];
100	u32 sig_detect_status;
101	u32 reserved13[3];
102	u32 sig_detect_status_clr;
103	u32 reserved14[3];
104
105	u32 sdmmc_det_counter;
106	u32 reserved15[(0x700 - 0x6b4) / 4];
107	u32 host0_con[3];
108	u32 reserved16[(0x880 - 0x70c) / 4];
109	u32 otg_con0;
110	u32 reserved17[3];
111	u32 host0_status;
112	u32 reserved18[(0x900 - 0x894) / 4];
113	u32 mac_con[3];
114	u32 reserved19[(0xb00 - 0x90c) / 4];
115	u32 macphy_con[4];
116	u32 macphy_status;
117	};
118	check_member(rk3328_grf_regs, macphy_status, 0xb10);
119
120	struct rk3328_sgrf_regs {
121	u32 soc_con[6];
122	u32 reserved0[(0x100 - 0x18) / 4];
123	u32 dmac_con[6];
124	u32 reserved1[(0x180 - 0x118) / 4];
125	u32 fast_boot_addr;
126	u32 reserved2[(0x200 - 0x184) / 4];
127	u32 chip_fuse_con;
128	u32 reserved3[(0x280 - 0x204) / 4];
129	u32 hdcp_key_reg[8];
130	u32 hdcp_key_access_mask;
131	};
132	check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
133
6f0c1237	134
d439a46e	135	#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */