[people/ms/u-boot.git] / arch / arm / include / asm / arch-rockchip / vop_rk3288.h

/*
 * Copyright (c) 2015 Google, Inc
 * Copyright 2014 Rockchip Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASM_ARCH_VOP_RK3288_H
#define _ASM_ARCH_VOP_RK3288_H

struct rk3288_vop {
	u32 reg_cfg_done;
	u32 version_info;
	u32 sys_ctrl;
	u32 sys_ctrl1;
	u32 dsp_ctrl0;
	u32 dsp_ctrl1;
	u32 dsp_bg;
	u32 mcu_ctrl;
	u32 intr_ctrl0;
	u32 intr_ctrl1;
	u32 intr_reserved0;
	u32 intr_reserved1;

	u32 win0_ctrl0;
	u32 win0_ctrl1;
	u32 win0_color_key;
	u32 win0_vir;
	u32 win0_yrgb_mst;
	u32 win0_cbr_mst;
	u32 win0_act_info;
	u32 win0_dsp_info;
	u32 win0_dsp_st;
	u32 win0_scl_factor_yrgb;
	u32 win0_scl_factor_cbr;
	u32 win0_scl_offset;
	u32 win0_src_alpha_ctrl;
	u32 win0_dst_alpha_ctrl;
	u32 win0_fading_ctrl;
	u32 win0_reserved0;

	u32 win1_ctrl0;
	u32 win1_ctrl1;
	u32 win1_color_key;
	u32 win1_vir;
	u32 win1_yrgb_mst;
	u32 win1_cbr_mst;
	u32 win1_act_info;
	u32 win1_dsp_info;
	u32 win1_dsp_st;
	u32 win1_scl_factor_yrgb;
	u32 win1_scl_factor_cbr;
	u32 win1_scl_offset;
	u32 win1_src_alpha_ctrl;
	u32 win1_dst_alpha_ctrl;
	u32 win1_fading_ctrl;
	u32 win1_reservd0;
	u32 reserved2[48];
	u32 post_dsp_hact_info;
	u32 post_dsp_vact_info;
	u32 post_scl_factor_yrgb;
	u32 post_reserved;
	u32 post_scl_ctrl;
	u32 post_dsp_vact_info_f1;
	u32 dsp_htotal_hs_end;
	u32 dsp_hact_st_end;
	u32 dsp_vtotal_vs_end;
	u32 dsp_vact_st_end;
	u32 dsp_vs_st_end_f1;
	u32 dsp_vact_st_end_f1;
};
check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);

enum rockchip_fb_data_format_t {
	ARGB8888 = 0,
	RGB888 = 1,
	RGB565 = 2,
};

enum {
	LB_YUV_3840X5 = 0x0,
	LB_YUV_2560X8 = 0x1,
	LB_RGB_3840X2 = 0x2,
	LB_RGB_2560X4 = 0x3,
	LB_RGB_1920X5 = 0x4,
	LB_RGB_1280X8 = 0x5
};

enum vop_modes {
	VOP_MODE_EDP = 0,
	VOP_MODE_HDMI,
	VOP_MODE_LVDS,
	VOP_MODE_NONE,
	VOP_MODE_AUTO_DETECT,
	VOP_MODE_UNKNOWN,
};

/* VOP_VERSION_INFO */
#define M_FPGA_VERSION (0xffff << 16)
#define M_RTL_VERSION  (0xffff)

/* VOP_SYS_CTRL */
#define M_AUTO_GATING_EN (1 << 23)
#define M_STANDBY_EN     (1 << 22)
#define M_DMA_STOP       (1 << 21)
#define M_MMU_EN         (1 << 20)
#define M_DAM_BURST_LENGTH (0x3 << 18)
#define M_MIPI_OUT_EN	   (1 << 15)
#define M_EDP_OUT_EN       (1 << 14)
#define M_HDMI_OUT_EN      (1 << 13)
#define M_RGB_OUT_EN       (1 << 12)
#define M_ALL_OUT_EN		\
		(M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN)
#define M_EDPI_WMS_FS      (1 << 10)
#define M_EDPI_WMS_MODE    (1 << 9)
#define M_EDPI_HALT_EN     (1 << 8)
#define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
#define M_DOUB_CHANNEL_EN     (1 << 3)
#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
#define M_DIRECT_PATH_EN       (1)

#define V_AUTO_GATING_EN(x) (((x) & 1) << 23)
#define V_STANDBY_EN(x)     (((x) & 1) << 22)
#define V_DMA_STOP(x)       (((x) & 1) << 21)
#define V_MMU_EN(x)         (((x) & 1) << 20)
#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18)
#define V_MIPI_OUT_EN(x)      (((x) & 1) << 15)
#define V_EDP_OUT_EN(x)       (((x) & 1) << 14)
#define V_HDMI_OUT_EN(x)      (((x) & 1) << 13)
#define V_RGB_OUT_EN(x)       (((x) & 1) << 12)
#define V_EDPI_WMS_FS(x)      (((x) & 1) << 10)
#define V_EDPI_WMS_MODE(x)    (((x) & 1) << 9)
#define V_EDPI_HALT_EN(x)     (((x)&1)<<8)
#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
#define V_DOUB_CHANNEL_EN(x)     (((x) & 1) << 3)
#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1)
#define V_DIRECT_PATH_EN(x)       ((x) & 1)

/* VOP_SYS_CTRL1 */
#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
#define M_AXI_MAX_OUTSTANDING_EN  (1 << 12)
#define M_NOC_WIN_QOS             (3 << 10)
#define M_NOC_QOS_EN              (1 << 9)
#define M_NOC_HURRY_THRESHOLD     (0x3f << 3)
#define M_NOC_HURRY_VALUE         (0x3 << 1)
#define M_NOC_HURRY_EN            (1)

#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13)
#define V_AXI_MAX_OUTSTANDING_EN(x)  (((x) & 1) << 12)
#define V_NOC_WIN_QOS(x)             (((x) & 3) << 10)
#define V_NOC_QOS_EN(x)              (((x) & 1) << 9)
#define V_NOC_HURRY_THRESHOLD(x)     (((x) & 0x3f) << 3)
#define V_NOC_HURRY_VALUE(x)         (((x) & 3) << 1)
#define V_NOC_HURRY_EN(x)            ((x) & 1)

/* VOP_DSP_CTRL0 */
#define M_DSP_Y_MIR_EN              (1 << 23)
#define M_DSP_X_MIR_EN              (1 << 22)
#define M_DSP_YUV_CLIP              (1 << 21)
#define M_DSP_CCIR656_AVG           (1 << 20)
#define M_DSP_BLACK_EN              (1 << 19)
#define M_DSP_BLANK_EN              (1 << 18)
#define M_DSP_OUT_ZERO              (1 << 17)
#define M_DSP_DUMMY_SWAP            (1 << 16)
#define M_DSP_DELTA_SWAP            (1 << 15)
#define M_DSP_RG_SWAP               (1 << 14)
#define M_DSP_RB_SWAP               (1 << 13)
#define M_DSP_BG_SWAP               (1 << 12)
#define M_DSP_FIELD_POL             (1 << 11)
#define M_DSP_INTERLACE             (1 << 10)
#define M_DSP_DDR_PHASE             (1 << 9)
#define M_DSP_DCLK_DDR              (1 << 8)
#define M_DSP_DCLK_POL              (1 << 7)
#define M_DSP_DEN_POL               (1 << 6)
#define M_DSP_VSYNC_POL             (1 << 5)
#define M_DSP_HSYNC_POL             (1 << 4)
#define M_DSP_OUT_MODE              (0xf)

#define V_DSP_Y_MIR_EN(x)              (((x) & 1) << 23)
#define V_DSP_X_MIR_EN(x)              (((x) & 1) << 22)
#define V_DSP_YUV_CLIP(x)              (((x) & 1) << 21)
#define V_DSP_CCIR656_AVG(x)           (((x) & 1) << 20)
#define V_DSP_BLACK_EN(x)              (((x) & 1) << 19)
#define V_DSP_BLANK_EN(x)              (((x) & 1) << 18)
#define V_DSP_OUT_ZERO(x)              (((x) & 1) << 17)
#define V_DSP_DUMMY_SWAP(x)            (((x) & 1) << 16)
#define V_DSP_DELTA_SWAP(x)            (((x) & 1) << 15)
#define V_DSP_RG_SWAP(x)               (((x) & 1) << 14)
#define V_DSP_RB_SWAP(x)               (((x) & 1) << 13)
#define V_DSP_BG_SWAP(x)               (((x) & 1) << 12)
#define V_DSP_FIELD_POL(x)             (((x) & 1) << 11)
#define V_DSP_INTERLACE(x)             (((x) & 1) << 10)
#define V_DSP_DDR_PHASE(x)             (((x) & 1) << 9)
#define V_DSP_DCLK_DDR(x)              (((x) & 1) << 8)
#define V_DSP_DCLK_POL(x)              (((x) & 1) << 7)
#define V_DSP_DEN_POL(x)               (((x) & 1) << 6)
#define V_DSP_VSYNC_POL(x)             (((x) & 1) << 5)
#define V_DSP_HSYNC_POL(x)             (((x) & 1) << 4)
#define V_DSP_OUT_MODE(x)              ((x) & 0xf)

/* VOP_DSP_CTRL1 */
#define M_DSP_LAYER3_SEL               (3 << 14)
#define M_DSP_LAYER2_SEL               (3 << 12)
#define M_DSP_LAYER1_SEL               (3 << 10)
#define M_DSP_LAYER0_SEL               (3 << 8)
#define M_DITHER_UP_EN                 (1 << 6)
#define M_DITHER_DOWN_SEL              (1 << 4)
#define M_DITHER_DOWN_MODE             (1 << 3)
#define M_DITHER_DOWN_EN               (1 << 2)
#define M_PRE_DITHER_DOWN_EN           (1 << 1)
#define M_DSP_LUT_EN                   (1)

#define V_DSP_LAYER3_SEL(x)                (((x) & 3) << 14)
#define V_DSP_LAYER2_SEL(x)                (((x) & 3) << 12)
#define V_DSP_LAYER1_SEL(x)                (((x) & 3) << 10)
#define V_DSP_LAYER0_SEL(x)                (((x) & 3) << 8)
#define V_DITHER_UP_EN(x)                  (((x) & 1) << 6)
#define V_DITHER_DOWN_SEL(x)               (((x) & 1) << 4)
#define V_DITHER_DOWN_MODE(x)              (((x) & 1) << 3)
#define V_DITHER_DOWN_EN(x)                (((x) & 1) << 2)
#define V_PRE_DITHER_DOWN_EN(x)            (((x) & 1) << 1)
#define V_DSP_LUT_EN(x)                    ((x)&1)

/* VOP_DSP_BG */
#define M_DSP_BG_RED     (0x3f << 20)
#define M_DSP_BG_GREEN   (0x3f << 10)
#define M_DSP_BG_BLUE    (0x3f << 0)

#define V_DSP_BG_RED(x)     (((x) & 0x3f) << 20)
#define V_DSP_BG_GREEN(x)   (((x) & 0x3f) << 10)
#define V_DSP_BG_BLUE(x)    (((x) & 0x3f) << 0)

/* VOP_WIN0_CTRL0 */
#define M_WIN0_YUV_CLIP     (1 << 20)
#define M_WIN0_CBR_DEFLICK  (1 << 19)
#define M_WIN0_YRGB_DEFLICK  (1 << 18)
#define M_WIN0_PPAS_ZERO_EN  (1 << 16)
#define M_WIN0_UV_SWAP       (1 << 15)
#define M_WIN0_MID_SWAP      (1 << 14)
#define M_WIN0_ALPHA_SWAP    (1 << 13)
#define M_WIN0_RB_SWAP       (1 << 12)
#define M_WIN0_CSC_MODE      (3 << 10)
#define M_WIN0_NO_OUTSTANDING (1 << 9)
#define M_WIN0_INTERLACE_READ  (1 << 8)
#define M_WIN0_LB_MODE         (7 << 5)
#define M_WIN0_FMT_10          (1 << 4)
#define M_WIN0_DATA_FMT        (7 << 1)
#define M_WIN0_EN              (1 << 0)

#define V_WIN0_YUV_CLIP(x)       (((x) & 1) << 20)
#define V_WIN0_CBR_DEFLICK(x)    (((x) & 1) << 19)
#define V_WIN0_YRGB_DEFLICK(x)   (((x) & 1) << 18)
#define V_WIN0_PPAS_ZERO_EN(x)   (((x) & 1) << 16)
#define V_WIN0_UV_SWAP(x)        (((x) & 1) << 15)
#define V_WIN0_MID_SWAP(x)       (((x) & 1) << 14)
#define V_WIN0_ALPHA_SWAP(x)     (((x) & 1) << 13)
#define V_WIN0_RB_SWAP(x)        (((x) & 1) << 12)
#define V_WIN0_CSC_MODE(x)       (((x) & 3) << 10)
#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9)
#define V_WIN0_INTERLACE_READ(x)  (((x) & 1) << 8)
#define V_WIN0_LB_MODE(x)         (((x) & 7) << 5)
#define V_WIN0_FMT_10(x)          (((x) & 1) << 4)
#define V_WIN0_DATA_FMT(x)        (((x) & 7) << 1)
#define V_WIN0_EN(x)              ((x) & 1)

/* VOP_WIN0_CTRL1 */
#define M_WIN0_CBR_VSD_MODE        (1 << 31)
#define M_WIN0_CBR_VSU_MODE        (1 << 30)
#define M_WIN0_CBR_HSD_MODE        (3 << 28)
#define M_WIN0_CBR_VER_SCL_MODE    (3 << 26)
#define M_WIN0_CBR_HOR_SCL_MODE    (3 << 24)
#define M_WIN0_YRGB_VSD_MODE       (1 << 23)
#define M_WIN0_YRGB_VSU_MODE       (1 << 22)
#define M_WIN0_YRGB_HSD_MODE       (3 << 20)
#define M_WIN0_YRGB_VER_SCL_MODE   (3 << 18)
#define M_WIN0_YRGB_HOR_SCL_MODE   (3 << 16)
#define M_WIN0_LINE_LOAD_MODE      (1 << 15)
#define M_WIN0_CBR_AXI_GATHER_NUM  (7 << 12)
#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8)
#define M_WIN0_VSD_CBR_GT2         (1 << 7)
#define M_WIN0_VSD_CBR_GT4         (1 << 6)
#define M_WIN0_VSD_YRGB_GT2        (1 << 5)
#define M_WIN0_VSD_YRGB_GT4        (1 << 4)
#define M_WIN0_BIC_COE_SEL         (3 << 2)
#define M_WIN0_CBR_AXI_GATHER_EN   (1 << 1)
#define M_WIN0_YRGB_AXI_GATHER_EN  (1)

#define V_WIN0_CBR_VSD_MODE(x)        (((x) & 1) << 31)
#define V_WIN0_CBR_VSU_MODE(x)        (((x) & 1) << 30)
#define V_WIN0_CBR_HSD_MODE(x)        (((x) & 3) << 28)
#define V_WIN0_CBR_VER_SCL_MODE(x)    (((x) & 3) << 26)
#define V_WIN0_CBR_HOR_SCL_MODE(x)    (((x) & 3) << 24)
#define V_WIN0_YRGB_VSD_MODE(x)       (((x) & 1) << 23)
#define V_WIN0_YRGB_VSU_MODE(x)       (((x) & 1) << 22)
#define V_WIN0_YRGB_HSD_MODE(x)       (((x) & 3) << 20)
#define V_WIN0_YRGB_VER_SCL_MODE(x)   (((x) & 3) << 18)
#define V_WIN0_YRGB_HOR_SCL_MODE(x)   (((x) & 3) << 16)
#define V_WIN0_LINE_LOAD_MODE(x)      (((x) & 1) << 15)
#define V_WIN0_CBR_AXI_GATHER_NUM(x)  (((x) & 7) << 12)
#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8)
#define V_WIN0_VSD_CBR_GT2(x)         (((x) & 1) << 7)
#define V_WIN0_VSD_CBR_GT4(x)         (((x) & 1) << 6)
#define V_WIN0_VSD_YRGB_GT2(x)        (((x) & 1) << 5)
#define V_WIN0_VSD_YRGB_GT4(x)        (((x) & 1) << 4)
#define V_WIN0_BIC_COE_SEL(x)         (((x) & 3) << 2)
#define V_WIN0_CBR_AXI_GATHER_EN(x)   (((x) & 1) << 1)
#define V_WIN0_YRGB_AXI_GATHER_EN(x)  ((x) & 1)

/*VOP_WIN0_COLOR_KEY*/
#define M_WIN0_KEY_EN                 (1 << 31)
#define M_WIN0_KEY_COLOR              (0x3fffffff)

#define V_WIN0_KEY_EN(x)              (((x) & 1) << 31)
#define V_WIN0_KEY_COLOR(x)           ((x) & 0x3fffffff)

/* VOP_WIN0_VIR */
#define V_ARGB888_VIRWIDTH(x)	(((x) & 0x3fff) << 0)
#define V_RGB888_VIRWIDTH(x)	(((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0)
#define V_RGB565_VIRWIDTH(x)	(((x / 2) & 0x3fff) << 0)
#define YUV_VIRWIDTH(x)		(((x / 4) & 0x3fff) << 0)

/* VOP_WIN0_ACT_INFO */
#define V_ACT_HEIGHT(x)         (((x) & 0x1fff) << 16)
#define V_ACT_WIDTH(x)          ((x) & 0x1fff)

/* VOP_WIN0_DSP_INFO */
#define V_DSP_HEIGHT(x)         (((x) & 0xfff) << 16)
#define V_DSP_WIDTH(x)          ((x) & 0xfff)

/* VOP_WIN0_DSP_ST */
#define V_DSP_YST(x)            (((x) & 0x1fff) << 16)
#define V_DSP_XST(x)            ((x) & 0x1fff)

/* VOP_WIN0_SCL_OFFSET */
#define V_WIN0_VS_OFFSET_CBR(x)     (((x) & 0xff) << 24)
#define V_WIN0_VS_OFFSET_YRGB(x)    (((x) & 0xff) << 16)
#define V_WIN0_HS_OFFSET_CBR(x)     (((x) & 0xff) << 8)
#define V_WIN0_HS_OFFSET_YRGB(x)    ((x) & 0xff)

#define V_HSYNC(x)		(((x)&0x1fff)<<0)   /* hsync pulse width */
#define V_HORPRD(x)		(((x)&0x1fff)<<16)   /* horizontal period */
#define V_VSYNC(x)		(((x)&0x1fff)<<0)
#define V_VERPRD(x)		(((x)&0x1fff)<<16)

#define V_HEAP(x)		(((x)&0x1fff)<<0)/* horizontal active end */
#define V_HASP(x)		(((x)&0x1fff)<<16)/* horizontal active start */
#define V_VAEP(x)		(((x)&0x1fff)<<0)
#define V_VASP(x)		(((x)&0x1fff)<<16)

#endif
Commit	Line	Data
7b7ad5c3 SG	1	/*
	2	* Copyright (c) 2015 Google, Inc
	3	* Copyright 2014 Rockchip Inc.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef _ASM_ARCH_VOP_RK3288_H
	9	#define _ASM_ARCH_VOP_RK3288_H
	10
	11	struct rk3288_vop {
	12	u32 reg_cfg_done;
	13	u32 version_info;
	14	u32 sys_ctrl;
	15	u32 sys_ctrl1;
	16	u32 dsp_ctrl0;
	17	u32 dsp_ctrl1;
	18	u32 dsp_bg;
	19	u32 mcu_ctrl;
	20	u32 intr_ctrl0;
	21	u32 intr_ctrl1;
	22	u32 intr_reserved0;
	23	u32 intr_reserved1;
	24
	25	u32 win0_ctrl0;
	26	u32 win0_ctrl1;
	27	u32 win0_color_key;
	28	u32 win0_vir;
	29	u32 win0_yrgb_mst;
	30	u32 win0_cbr_mst;
	31	u32 win0_act_info;
	32	u32 win0_dsp_info;
	33	u32 win0_dsp_st;
	34	u32 win0_scl_factor_yrgb;
	35	u32 win0_scl_factor_cbr;
	36	u32 win0_scl_offset;
	37	u32 win0_src_alpha_ctrl;
	38	u32 win0_dst_alpha_ctrl;
	39	u32 win0_fading_ctrl;
	40	u32 win0_reserved0;
	41
	42	u32 win1_ctrl0;
	43	u32 win1_ctrl1;
	44	u32 win1_color_key;
	45	u32 win1_vir;
	46	u32 win1_yrgb_mst;
	47	u32 win1_cbr_mst;
	48	u32 win1_act_info;
	49	u32 win1_dsp_info;
	50	u32 win1_dsp_st;
	51	u32 win1_scl_factor_yrgb;
	52	u32 win1_scl_factor_cbr;
	53	u32 win1_scl_offset;
	54	u32 win1_src_alpha_ctrl;
	55	u32 win1_dst_alpha_ctrl;
	56	u32 win1_fading_ctrl;
	57	u32 win1_reservd0;
	58	u32 reserved2[48];
	59	u32 post_dsp_hact_info;
	60	u32 post_dsp_vact_info;
	61	u32 post_scl_factor_yrgb;
	62	u32 post_reserved;
	63	u32 post_scl_ctrl;
	64	u32 post_dsp_vact_info_f1;
65	u32 dsp_htotal_hs_end;
66	u32 dsp_hact_st_end;
67	u32 dsp_vtotal_vs_end;
68	u32 dsp_vact_st_end;
69	u32 dsp_vs_st_end_f1;
70	u32 dsp_vact_st_end_f1;
71	};
72	check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
73
74	enum rockchip_fb_data_format_t {
75	ARGB8888 = 0,
76	RGB888 = 1,
77	RGB565 = 2,
78	};
79
80	enum {
81	LB_YUV_3840X5 = 0x0,
82	LB_YUV_2560X8 = 0x1,
83	LB_RGB_3840X2 = 0x2,
84	LB_RGB_2560X4 = 0x3,
85	LB_RGB_1920X5 = 0x4,
86	LB_RGB_1280X8 = 0x5
87	};
88
89	enum vop_modes {
90	VOP_MODE_EDP = 0,
91	VOP_MODE_HDMI,
85307835	92	VOP_MODE_LVDS,
7b7ad5c3 SG	93	VOP_MODE_NONE,
	94	VOP_MODE_AUTO_DETECT,
	95	VOP_MODE_UNKNOWN,
	96	};
	97
	98	/* VOP_VERSION_INFO */
	99	#define M_FPGA_VERSION (0xffff << 16)
	100	#define M_RTL_VERSION (0xffff)
	101
	102	/* VOP_SYS_CTRL */
	103	#define M_AUTO_GATING_EN (1 << 23)
	104	#define M_STANDBY_EN (1 << 22)
	105	#define M_DMA_STOP (1 << 21)
	106	#define M_MMU_EN (1 << 20)
	107	#define M_DAM_BURST_LENGTH (0x3 << 18)
	108	#define M_MIPI_OUT_EN (1 << 15)
	109	#define M_EDP_OUT_EN (1 << 14)
	110	#define M_HDMI_OUT_EN (1 << 13)
	111	#define M_RGB_OUT_EN (1 << 12)
	112	#define M_ALL_OUT_EN \
	113	(M_MIPI_OUT_EN \| M_EDP_OUT_EN \| M_HDMI_OUT_EN \| M_RGB_OUT_EN)
	114	#define M_EDPI_WMS_FS (1 << 10)
	115	#define M_EDPI_WMS_MODE (1 << 9)
	116	#define M_EDPI_HALT_EN (1 << 8)
	117	#define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
	118	#define M_DOUB_CHANNEL_EN (1 << 3)
	119	#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
	120	#define M_DIRECT_PATH_EN (1)
	121
	122	#define V_AUTO_GATING_EN(x) (((x) & 1) << 23)
	123	#define V_STANDBY_EN(x) (((x) & 1) << 22)
	124	#define V_DMA_STOP(x) (((x) & 1) << 21)
	125	#define V_MMU_EN(x) (((x) & 1) << 20)
	126	#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18)
	127	#define V_MIPI_OUT_EN(x) (((x) & 1) << 15)
	128	#define V_EDP_OUT_EN(x) (((x) & 1) << 14)
	129	#define V_HDMI_OUT_EN(x) (((x) & 1) << 13)
	130	#define V_RGB_OUT_EN(x) (((x) & 1) << 12)
	131	#define V_EDPI_WMS_FS(x) (((x) & 1) << 10)
	132	#define V_EDPI_WMS_MODE(x) (((x) & 1) << 9)
	133	#define V_EDPI_HALT_EN(x) (((x)&1)<<8)
	134	#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
	135	#define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3)
	136	#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1)
	137	#define V_DIRECT_PATH_EN(x) ((x) & 1)
	138
	139	/* VOP_SYS_CTRL1 */
	140	#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
	141	#define M_AXI_MAX_OUTSTANDING_EN (1 << 12)
	142	#define M_NOC_WIN_QOS (3 << 10)
	143	#define M_NOC_QOS_EN (1 << 9)
	144	#define M_NOC_HURRY_THRESHOLD (0x3f << 3)
	145	#define M_NOC_HURRY_VALUE (0x3 << 1)
	146	#define M_NOC_HURRY_EN (1)
	147
	148	#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13)
	149	#define V_AXI_MAX_OUTSTANDING_EN(x) (((x) & 1) << 12)
	150	#define V_NOC_WIN_QOS(x) (((x) & 3) << 10)
	151	#define V_NOC_QOS_EN(x) (((x) & 1) << 9)
	152	#define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3)
	153	#define V_NOC_HURRY_VALUE(x) (((x) & 3) << 1)
	154	#define V_NOC_HURRY_EN(x) ((x) & 1)
	155
	156	/* VOP_DSP_CTRL0 */
157	#define M_DSP_Y_MIR_EN (1 << 23)
158	#define M_DSP_X_MIR_EN (1 << 22)
159	#define M_DSP_YUV_CLIP (1 << 21)
160	#define M_DSP_CCIR656_AVG (1 << 20)
161	#define M_DSP_BLACK_EN (1 << 19)
162	#define M_DSP_BLANK_EN (1 << 18)
163	#define M_DSP_OUT_ZERO (1 << 17)
164	#define M_DSP_DUMMY_SWAP (1 << 16)
165	#define M_DSP_DELTA_SWAP (1 << 15)
166	#define M_DSP_RG_SWAP (1 << 14)
167	#define M_DSP_RB_SWAP (1 << 13)
168	#define M_DSP_BG_SWAP (1 << 12)
169	#define M_DSP_FIELD_POL (1 << 11)
170	#define M_DSP_INTERLACE (1 << 10)
171	#define M_DSP_DDR_PHASE (1 << 9)
172	#define M_DSP_DCLK_DDR (1 << 8)
173	#define M_DSP_DCLK_POL (1 << 7)
174	#define M_DSP_DEN_POL (1 << 6)
175	#define M_DSP_VSYNC_POL (1 << 5)
176	#define M_DSP_HSYNC_POL (1 << 4)
177	#define M_DSP_OUT_MODE (0xf)
178
179	#define V_DSP_Y_MIR_EN(x) (((x) & 1) << 23)
180	#define V_DSP_X_MIR_EN(x) (((x) & 1) << 22)
181	#define V_DSP_YUV_CLIP(x) (((x) & 1) << 21)
182	#define V_DSP_CCIR656_AVG(x) (((x) & 1) << 20)
183	#define V_DSP_BLACK_EN(x) (((x) & 1) << 19)
184	#define V_DSP_BLANK_EN(x) (((x) & 1) << 18)
185	#define V_DSP_OUT_ZERO(x) (((x) & 1) << 17)
186	#define V_DSP_DUMMY_SWAP(x) (((x) & 1) << 16)
187	#define V_DSP_DELTA_SWAP(x) (((x) & 1) << 15)
188	#define V_DSP_RG_SWAP(x) (((x) & 1) << 14)
189	#define V_DSP_RB_SWAP(x) (((x) & 1) << 13)
190	#define V_DSP_BG_SWAP(x) (((x) & 1) << 12)
191	#define V_DSP_FIELD_POL(x) (((x) & 1) << 11)
192	#define V_DSP_INTERLACE(x) (((x) & 1) << 10)
193	#define V_DSP_DDR_PHASE(x) (((x) & 1) << 9)
194	#define V_DSP_DCLK_DDR(x) (((x) & 1) << 8)
195	#define V_DSP_DCLK_POL(x) (((x) & 1) << 7)
196	#define V_DSP_DEN_POL(x) (((x) & 1) << 6)
197	#define V_DSP_VSYNC_POL(x) (((x) & 1) << 5)
198	#define V_DSP_HSYNC_POL(x) (((x) & 1) << 4)
199	#define V_DSP_OUT_MODE(x) ((x) & 0xf)
200
201	/* VOP_DSP_CTRL1 */
202	#define M_DSP_LAYER3_SEL (3 << 14)
203	#define M_DSP_LAYER2_SEL (3 << 12)
204	#define M_DSP_LAYER1_SEL (3 << 10)
205	#define M_DSP_LAYER0_SEL (3 << 8)
206	#define M_DITHER_UP_EN (1 << 6)
207	#define M_DITHER_DOWN_SEL (1 << 4)
208	#define M_DITHER_DOWN_MODE (1 << 3)
209	#define M_DITHER_DOWN_EN (1 << 2)
210	#define M_PRE_DITHER_DOWN_EN (1 << 1)
211	#define M_DSP_LUT_EN (1)
212
213	#define V_DSP_LAYER3_SEL(x) (((x) & 3) << 14)
214	#define V_DSP_LAYER2_SEL(x) (((x) & 3) << 12)
215	#define V_DSP_LAYER1_SEL(x) (((x) & 3) << 10)
216	#define V_DSP_LAYER0_SEL(x) (((x) & 3) << 8)
217	#define V_DITHER_UP_EN(x) (((x) & 1) << 6)
218	#define V_DITHER_DOWN_SEL(x) (((x) & 1) << 4)
219	#define V_DITHER_DOWN_MODE(x) (((x) & 1) << 3)
220	#define V_DITHER_DOWN_EN(x) (((x) & 1) << 2)
221	#define V_PRE_DITHER_DOWN_EN(x) (((x) & 1) << 1)
222	#define V_DSP_LUT_EN(x) ((x)&1)
223
224	/* VOP_DSP_BG */
225	#define M_DSP_BG_RED (0x3f << 20)
226	#define M_DSP_BG_GREEN (0x3f << 10)
227	#define M_DSP_BG_BLUE (0x3f << 0)
228
229	#define V_DSP_BG_RED(x) (((x) & 0x3f) << 20)
230	#define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10)
231	#define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0)
232
233	/* VOP_WIN0_CTRL0 */
234	#define M_WIN0_YUV_CLIP (1 << 20)
235	#define M_WIN0_CBR_DEFLICK (1 << 19)
236	#define M_WIN0_YRGB_DEFLICK (1 << 18)
237	#define M_WIN0_PPAS_ZERO_EN (1 << 16)
238	#define M_WIN0_UV_SWAP (1 << 15)
239	#define M_WIN0_MID_SWAP (1 << 14)
240	#define M_WIN0_ALPHA_SWAP (1 << 13)
241	#define M_WIN0_RB_SWAP (1 << 12)
242	#define M_WIN0_CSC_MODE (3 << 10)
243	#define M_WIN0_NO_OUTSTANDING (1 << 9)
244	#define M_WIN0_INTERLACE_READ (1 << 8)
245	#define M_WIN0_LB_MODE (7 << 5)
246	#define M_WIN0_FMT_10 (1 << 4)
247	#define M_WIN0_DATA_FMT (7 << 1)
248	#define M_WIN0_EN (1 << 0)
249
250	#define V_WIN0_YUV_CLIP(x) (((x) & 1) << 20)
251	#define V_WIN0_CBR_DEFLICK(x) (((x) & 1) << 19)
252	#define V_WIN0_YRGB_DEFLICK(x) (((x) & 1) << 18)
253	#define V_WIN0_PPAS_ZERO_EN(x) (((x) & 1) << 16)
254	#define V_WIN0_UV_SWAP(x) (((x) & 1) << 15)
255	#define V_WIN0_MID_SWAP(x) (((x) & 1) << 14)
256	#define V_WIN0_ALPHA_SWAP(x) (((x) & 1) << 13)
257	#define V_WIN0_RB_SWAP(x) (((x) & 1) << 12)
258	#define V_WIN0_CSC_MODE(x) (((x) & 3) << 10)
259	#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9)
260	#define V_WIN0_INTERLACE_READ(x) (((x) & 1) << 8)
261	#define V_WIN0_LB_MODE(x) (((x) & 7) << 5)
262	#define V_WIN0_FMT_10(x) (((x) & 1) << 4)
263	#define V_WIN0_DATA_FMT(x) (((x) & 7) << 1)
264	#define V_WIN0_EN(x) ((x) & 1)
265
266	/* VOP_WIN0_CTRL1 */
267	#define M_WIN0_CBR_VSD_MODE (1 << 31)
268	#define M_WIN0_CBR_VSU_MODE (1 << 30)
269	#define M_WIN0_CBR_HSD_MODE (3 << 28)
270	#define M_WIN0_CBR_VER_SCL_MODE (3 << 26)
271	#define M_WIN0_CBR_HOR_SCL_MODE (3 << 24)
272	#define M_WIN0_YRGB_VSD_MODE (1 << 23)
273	#define M_WIN0_YRGB_VSU_MODE (1 << 22)
274	#define M_WIN0_YRGB_HSD_MODE (3 << 20)
275	#define M_WIN0_YRGB_VER_SCL_MODE (3 << 18)
276	#define M_WIN0_YRGB_HOR_SCL_MODE (3 << 16)
277	#define M_WIN0_LINE_LOAD_MODE (1 << 15)
278	#define M_WIN0_CBR_AXI_GATHER_NUM (7 << 12)
279	#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8)
280	#define M_WIN0_VSD_CBR_GT2 (1 << 7)
281	#define M_WIN0_VSD_CBR_GT4 (1 << 6)
282	#define M_WIN0_VSD_YRGB_GT2 (1 << 5)
283	#define M_WIN0_VSD_YRGB_GT4 (1 << 4)
284	#define M_WIN0_BIC_COE_SEL (3 << 2)
285	#define M_WIN0_CBR_AXI_GATHER_EN (1 << 1)
286	#define M_WIN0_YRGB_AXI_GATHER_EN (1)
287
288	#define V_WIN0_CBR_VSD_MODE(x) (((x) & 1) << 31)
289	#define V_WIN0_CBR_VSU_MODE(x) (((x) & 1) << 30)
290	#define V_WIN0_CBR_HSD_MODE(x) (((x) & 3) << 28)
291	#define V_WIN0_CBR_VER_SCL_MODE(x) (((x) & 3) << 26)
292	#define V_WIN0_CBR_HOR_SCL_MODE(x) (((x) & 3) << 24)
293	#define V_WIN0_YRGB_VSD_MODE(x) (((x) & 1) << 23)
294	#define V_WIN0_YRGB_VSU_MODE(x) (((x) & 1) << 22)
295	#define V_WIN0_YRGB_HSD_MODE(x) (((x) & 3) << 20)
296	#define V_WIN0_YRGB_VER_SCL_MODE(x) (((x) & 3) << 18)
297	#define V_WIN0_YRGB_HOR_SCL_MODE(x) (((x) & 3) << 16)
298	#define V_WIN0_LINE_LOAD_MODE(x) (((x) & 1) << 15)
299	#define V_WIN0_CBR_AXI_GATHER_NUM(x) (((x) & 7) << 12)
300	#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8)
301	#define V_WIN0_VSD_CBR_GT2(x) (((x) & 1) << 7)
302	#define V_WIN0_VSD_CBR_GT4(x) (((x) & 1) << 6)
303	#define V_WIN0_VSD_YRGB_GT2(x) (((x) & 1) << 5)
304	#define V_WIN0_VSD_YRGB_GT4(x) (((x) & 1) << 4)
305	#define V_WIN0_BIC_COE_SEL(x) (((x) & 3) << 2)
306	#define V_WIN0_CBR_AXI_GATHER_EN(x) (((x) & 1) << 1)
307	#define V_WIN0_YRGB_AXI_GATHER_EN(x) ((x) & 1)
308
309	/VOP_WIN0_COLOR_KEY/
310	#define M_WIN0_KEY_EN (1 << 31)
311	#define M_WIN0_KEY_COLOR (0x3fffffff)
312
313	#define V_WIN0_KEY_EN(x) (((x) & 1) << 31)
314	#define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff)
315
316	/* VOP_WIN0_VIR */
317	#define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0)
318	#define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0)
319	#define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0)
320	#define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0)
321
322	/* VOP_WIN0_ACT_INFO */
323	#define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16)
324	#define V_ACT_WIDTH(x) ((x) & 0x1fff)
325
326	/* VOP_WIN0_DSP_INFO */
327	#define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16)
328	#define V_DSP_WIDTH(x) ((x) & 0xfff)
329
330	/* VOP_WIN0_DSP_ST */
331	#define V_DSP_YST(x) (((x) & 0x1fff) << 16)
332	#define V_DSP_XST(x) ((x) & 0x1fff)
333
334	/* VOP_WIN0_SCL_OFFSET */
335	#define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24)
336	#define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16)
337	#define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8)
338	#define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff)
339
340	#define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */
341	#define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */
342	#define V_VSYNC(x) (((x)&0x1fff)<<0)
343	#define V_VERPRD(x) (((x)&0x1fff)<<16)
344
345	#define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */
346	#define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */
347	#define V_VAEP(x) (((x)&0x1fff)<<0)
348	#define V_VASP(x) (((x)&0x1fff)<<16)
349
350	#endif