[people/ms/u-boot.git] / arch / arm / include / asm / arch-s3c24x0 / s3c24x0.h

/*
 * (C) Copyright 2003
 * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************
 * NAME	    : s3c24x0.h
 * Version  : 31.3.2003
 *
 * common stuff for SAMSUNG S3C24X0 SoC
 ************************************************/

#ifndef __S3C24X0_H__
#define __S3C24X0_H__

/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
	u32	bwscon;
	u32	bankcon[8];
	u32	refresh;
	u32	banksize;
	u32	mrsrb6;
	u32	mrsrb7;
};


/* USB HOST (see manual chapter 12) */
struct s3c24x0_usb_host {
	u32	HcRevision;
	u32	HcControl;
	u32	HcCommonStatus;
	u32	HcInterruptStatus;
	u32	HcInterruptEnable;
	u32	HcInterruptDisable;
	u32	HcHCCA;
	u32	HcPeriodCuttendED;
	u32	HcControlHeadED;
	u32	HcControlCurrentED;
	u32	HcBulkHeadED;
	u32	HcBuldCurrentED;
	u32	HcDoneHead;
	u32	HcRmInterval;
	u32	HcFmRemaining;
	u32	HcFmNumber;
	u32	HcPeriodicStart;
	u32	HcLSThreshold;
	u32	HcRhDescriptorA;
	u32	HcRhDescriptorB;
	u32	HcRhStatus;
	u32	HcRhPortStatus1;
	u32	HcRhPortStatus2;
};


/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
	u32	srcpnd;
	u32	intmod;
	u32	intmsk;
	u32	priority;
	u32	intpnd;
	u32	intoffset;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
	u32	subsrcpnd;
	u32	intsubmsk;
#endif
};


/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
	u32	disrc;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
	u32	disrcc;
#endif
	u32	didst;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
	u32	didstc;
#endif
	u32	dcon;
	u32	dstat;
	u32	dcsrc;
	u32	dcdst;
	u32	dmasktrig;
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
		|| defined(CONFIG_S3C2440)
	u32	res[1];
#endif
};

struct s3c24x0_dmas {
	struct s3c24x0_dma	dma[4];
};


/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/*                          (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
	u32	locktime;
	u32	mpllcon;
	u32	upllcon;
	u32	clkcon;
	u32	clkslow;
	u32	clkdivn;
#if defined(CONFIG_S3C2440)
	u32	camdivn;
#endif
};


/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
	u32	lcdcon1;
	u32	lcdcon2;
	u32	lcdcon3;
	u32	lcdcon4;
	u32	lcdcon5;
	u32	lcdsaddr1;
	u32	lcdsaddr2;
	u32	lcdsaddr3;
	u32	redlut;
	u32	greenlut;
	u32	bluelut;
	u32	res[8];
	u32	dithmode;
	u32	tpal;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
	u32	lcdintpnd;
	u32	lcdsrcpnd;
	u32	lcdintmsk;
	u32	lpcsel;
#endif
};


#ifdef CONFIG_S3C2410
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
	u32	nfconf;
	u32	nfcmd;
	u32	nfaddr;
	u32	nfdata;
	u32	nfstat;
	u32	nfecc;
};
#endif
#ifdef CONFIG_S3C2440
/* NAND FLASH (see S3C2440 manual chapter 6) */
struct s3c2440_nand {
	u32	nfconf;
	u32	nfcont;
	u32	nfcmd;
	u32	nfaddr;
	u32	nfdata;
	u32	nfeccd0;
	u32	nfeccd1;
	u32	nfeccd;
	u32	nfstat;
	u32	nfstat0;
	u32	nfstat1;
};
#endif


/* UART (see manual chapter 11) */
struct s3c24x0_uart {
	u32	ulcon;
	u32	ucon;
	u32	ufcon;
	u32	umcon;
	u32	utrstat;
	u32	uerstat;
	u32	ufstat;
	u32	umstat;
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	utxh;
	u8	res2[3];
	u8	urxh;
#else /* Little Endian */
	u8	utxh;
	u8	res1[3];
	u8	urxh;
	u8	res2[3];
#endif
	u32	ubrdiv;
};


/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
	u32	tcntb;
	u32	tcmpb;
	u32	tcnto;
};

struct s3c24x0_timers {
	u32	tcfg0;
	u32	tcfg1;
	u32	tcon;
	struct s3c24x0_timer	ch[4];
	u32	tcntb4;
	u32	tcnto4;
};


/* USB DEVICE (see manual chapter 13) */
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
	u8	res[3];
	u8	ep_fifo_reg;
#else /*  little endian */
	u8	ep_fifo_reg;
	u8	res[3];
#endif
};

struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	ep_dma_con;
	u8	res2[3];
	u8	ep_dma_unit;
	u8	res3[3];
	u8	ep_dma_fifo;
	u8	res4[3];
	u8	ep_dma_ttc_l;
	u8	res5[3];
	u8	ep_dma_ttc_m;
	u8	res6[3];
	u8	ep_dma_ttc_h;
#else /*  little endian */
	u8	ep_dma_con;
	u8	res1[3];
	u8	ep_dma_unit;
	u8	res2[3];
	u8	ep_dma_fifo;
	u8	res3[3];
	u8	ep_dma_ttc_l;
	u8	res4[3];
	u8	ep_dma_ttc_m;
	u8	res5[3];
	u8	ep_dma_ttc_h;
	u8	res6[3];
#endif
};

struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	func_addr_reg;
	u8	res2[3];
	u8	pwr_reg;
	u8	res3[3];
	u8	ep_int_reg;
	u8	res4[15];
	u8	usb_int_reg;
	u8	res5[3];
	u8	ep_int_en_reg;
	u8	res6[15];
	u8	usb_int_en_reg;
	u8	res7[3];
	u8	frame_num1_reg;
	u8	res8[3];
	u8	frame_num2_reg;
	u8	res9[3];
	u8	index_reg;
	u8	res10[7];
	u8	maxp_reg;
	u8	res11[3];
	u8	ep0_csr_in_csr1_reg;
	u8	res12[3];
	u8	in_csr2_reg;
	u8	res13[7];
	u8	out_csr1_reg;
	u8	res14[3];
	u8	out_csr2_reg;
	u8	res15[3];
	u8	out_fifo_cnt1_reg;
	u8	res16[3];
	u8	out_fifo_cnt2_reg;
#else /*  little endian */
	u8	func_addr_reg;
	u8	res1[3];
	u8	pwr_reg;
	u8	res2[3];
	u8	ep_int_reg;
	u8	res3[15];
	u8	usb_int_reg;
	u8	res4[3];
	u8	ep_int_en_reg;
	u8	res5[15];
	u8	usb_int_en_reg;
	u8	res6[3];
	u8	frame_num1_reg;
	u8	res7[3];
	u8	frame_num2_reg;
	u8	res8[3];
	u8	index_reg;
	u8	res9[7];
	u8	maxp_reg;
	u8	res10[7];
	u8	ep0_csr_in_csr1_reg;
	u8	res11[3];
	u8	in_csr2_reg;
	u8	res12[3];
	u8	out_csr1_reg;
	u8	res13[7];
	u8	out_csr2_reg;
	u8	res14[3];
	u8	out_fifo_cnt1_reg;
	u8	res15[3];
	u8	out_fifo_cnt2_reg;
	u8	res16[3];
#endif /*  __BIG_ENDIAN */
	struct s3c24x0_usb_dev_fifos	fifo[5];
	struct s3c24x0_usb_dev_dmas	dma[5];
};


/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
	u32	wtcon;
	u32	wtdat;
	u32	wtcnt;
};

/* IIS (see manual chapter 21) */
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
	u16	res1;
	u16	iiscon;
	u16	res2;
	u16	iismod;
	u16	res3;
	u16	iispsr;
	u16	res4;
	u16	iisfcon;
	u16	res5;
	u16	iisfifo;
#else /*  little endian */
	u16	iiscon;
	u16	res1;
	u16	iismod;
	u16	res2;
	u16	iispsr;
	u16	res3;
	u16	iisfcon;
	u16	res4;
	u16	iisfifo;
	u16	res5;
#endif
};


/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
	u32	pacon;
	u32	padat;

	u32	pbcon;
	u32	pbdat;
	u32	pbup;

	u32	pccon;
	u32	pcdat;
	u32	pcup;

	u32	pdcon;
	u32	pddat;
	u32	pdup;

	u32	pecon;
	u32	pedat;
	u32	peup;

	u32	pfcon;
	u32	pfdat;
	u32	pfup;

	u32	pgcon;
	u32	pgdat;
	u32	pgup;

	u32	opencr;

	u32	misccr;
	u32	extint;
#endif
#ifdef CONFIG_S3C2410
	u32	gpacon;
	u32	gpadat;
	u32	res1[2];
	u32	gpbcon;
	u32	gpbdat;
	u32	gpbup;
	u32	res2;
	u32	gpccon;
	u32	gpcdat;
	u32	gpcup;
	u32	res3;
	u32	gpdcon;
	u32	gpddat;
	u32	gpdup;
	u32	res4;
	u32	gpecon;
	u32	gpedat;
	u32	gpeup;
	u32	res5;
	u32	gpfcon;
	u32	gpfdat;
	u32	gpfup;
	u32	res6;
	u32	gpgcon;
	u32	gpgdat;
	u32	gpgup;
	u32	res7;
	u32	gphcon;
	u32	gphdat;
	u32	gphup;
	u32	res8;

	u32	misccr;
	u32	dclkcon;
	u32	extint0;
	u32	extint1;
	u32	extint2;
	u32	eintflt0;
	u32	eintflt1;
	u32	eintflt2;
	u32	eintflt3;
	u32	eintmask;
	u32	eintpend;
	u32	gstatus0;
	u32	gstatus1;
	u32	gstatus2;
	u32	gstatus3;
	u32	gstatus4;
#endif
#if defined(CONFIG_S3C2440)
	u32	gpacon;
	u32	gpadat;
	u32	res1[2];
	u32	gpbcon;
	u32	gpbdat;
	u32	gpbup;
	u32	res2;
	u32	gpccon;
	u32	gpcdat;
	u32	gpcup;
	u32	res3;
	u32	gpdcon;
	u32	gpddat;
	u32	gpdup;
	u32	res4;
	u32	gpecon;
	u32	gpedat;
	u32	gpeup;
	u32	res5;
	u32	gpfcon;
	u32	gpfdat;
	u32	gpfup;
	u32	res6;
	u32	gpgcon;
	u32	gpgdat;
	u32	gpgup;
	u32	res7;
	u32	gphcon;
	u32	gphdat;
	u32	gphup;
	u32	res8;

	u32	misccr;
	u32	dclkcon;
	u32	extint0;
	u32	extint1;
	u32	extint2;
	u32	eintflt0;
	u32	eintflt1;
	u32	eintflt2;
	u32	eintflt3;
	u32	eintmask;
	u32	eintpend;
	u32	gstatus0;
	u32	gstatus1;
	u32	gstatus2;
	u32	gstatus3;
	u32	gstatus4;

	u32	res9;
	u32	dsc0;
	u32	dsc1;
	u32	mslcon;
	u32	gpjcon;
	u32	gpjdat;
	u32	gpjup;
	u32	res10;
#endif
};


/* RTC (see manual chapter 17) */
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
	u8	res1[67];
	u8	rtccon;
	u8	res2[3];
	u8	ticnt;
	u8	res3[11];
	u8	rtcalm;
	u8	res4[3];
	u8	almsec;
	u8	res5[3];
	u8	almmin;
	u8	res6[3];
	u8	almhour;
	u8	res7[3];
	u8	almdate;
	u8	res8[3];
	u8	almmon;
	u8	res9[3];
	u8	almyear;
	u8	res10[3];
	u8	rtcrst;
	u8	res11[3];
	u8	bcdsec;
	u8	res12[3];
	u8	bcdmin;
	u8	res13[3];
	u8	bcdhour;
	u8	res14[3];
	u8	bcddate;
	u8	res15[3];
	u8	bcdday;
	u8	res16[3];
	u8	bcdmon;
	u8	res17[3];
	u8	bcdyear;
#else /*  little endian */
	u8	res0[64];
	u8	rtccon;
	u8	res1[3];
	u8	ticnt;
	u8	res2[11];
	u8	rtcalm;
	u8	res3[3];
	u8	almsec;
	u8	res4[3];
	u8	almmin;
	u8	res5[3];
	u8	almhour;
	u8	res6[3];
	u8	almdate;
	u8	res7[3];
	u8	almmon;
	u8	res8[3];
	u8	almyear;
	u8	res9[3];
	u8	rtcrst;
	u8	res10[3];
	u8	bcdsec;
	u8	res11[3];
	u8	bcdmin;
	u8	res12[3];
	u8	bcdhour;
	u8	res13[3];
	u8	bcddate;
	u8	res14[3];
	u8	bcdday;
	u8	res15[3];
	u8	bcdmon;
	u8	res16[3];
	u8	bcdyear;
	u8	res17[3];
#endif
};


/* ADC (see manual chapter 16) */
struct s3c2400_adc {
	u32	adccon;
	u32	adcdat;
};


/* ADC (see manual chapter 16) */
struct s3c2410_adc {
	u32	adccon;
	u32	adctsc;
	u32	adcdly;
	u32	adcdat0;
	u32	adcdat1;
};


/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
	u8	spcon;
	u8	res1[3];
	u8	spsta;
	u8	res2[3];
	u8	sppin;
	u8	res3[3];
	u8	sppre;
	u8	res4[3];
	u8	sptdat;
	u8	res5[3];
	u8	sprdat;
	u8	res6[3];
	u8	res7[16];
};

struct s3c24x0_spi {
	struct s3c24x0_spi_channel	ch[S3C24X0_SPI_CHANNELS];
};


/* MMC INTERFACE (see S3C2400 manual chapter 19) */
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
	u8	res1[3];
	u8	mmcon;
	u8	res2[3];
	u8	mmcrr;
	u8	res3[3];
	u8	mmfcon;
	u8	res4[3];
	u8	mmsta;
	u16	res5;
	u16	mmfsta;
	u8	res6[3];
	u8	mmpre;
	u16	res7;
	u16	mmlen;
	u8	res8[3];
	u8	mmcr7;
	u32	mmrsp[4];
	u8	res9[3];
	u8	mmcmd0;
	u32	mmcmd1;
	u16	res10;
	u16	mmcr16;
	u8	res11[3];
	u8	mmdat;
#else
	u8	mmcon;
	u8	res1[3];
	u8	mmcrr;
	u8	res2[3];
	u8	mmfcon;
	u8	res3[3];
	u8	mmsta;
	u8	res4[3];
	u16	mmfsta;
	u16	res5;
	u8	mmpre;
	u8	res6[3];
	u16	mmlen;
	u16	res7;
	u8	mmcr7;
	u8	res8[3];
	u32	mmrsp[4];
	u8	mmcmd0;
	u8	res9[3];
	u32	mmcmd1;
	u16	mmcr16;
	u16	res10;
	u8	mmdat;
	u8	res11[3];
#endif
};


/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
	u32	sdicon;
	u32	sdipre;
	u32	sdicarg;
	u32	sdiccon;
	u32	sdicsta;
	u32	sdirsp0;
	u32	sdirsp1;
	u32	sdirsp2;
	u32	sdirsp3;
	u32	sdidtimer;
	u32	sdibsize;
	u32	sdidcon;
	u32	sdidcnt;
	u32	sdidsta;
	u32	sdifsta;
#ifdef __BIG_ENDIAN
	u8	res[3];
	u8	sdidat;
#else
	u8	sdidat;
	u8	res[3];
#endif
	u32	sdiimsk;
};

#endif /*__S3C24X0_H__*/
Commit	Line	Data
48b42616 WD	1	/*
48b42616 WD	2	* (C) Copyright 2003
fa82f871	3	* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
48b42616	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
48b42616 WD	6	*/
	7
	8	/************************************************
	9	* NAME : s3c24x0.h
	10	* Version : 31.3.2003
	11	*
	12	* common stuff for SAMSUNG S3C24X0 SoC
	13	************************************************/
	14
	15	#ifndef __S3C24X0_H__
	16	#define __S3C24X0_H__
	17
48b42616	18	/* Memory controller (see manual chapter 5) */
8250d0ba	19	struct s3c24x0_memctl {
d9abba82 N	20	u32 bwscon;
	21	u32 bankcon[8];
	22	u32 refresh;
	23	u32 banksize;
	24	u32 mrsrb6;
	25	u32 mrsrb7;
8250d0ba	26	};
48b42616 WD	27
	28
	29	/* USB HOST (see manual chapter 12) */
8250d0ba	30	struct s3c24x0_usb_host {
9ebfdc20	31	u32 HcRevision;
	32	u32 HcControl;
	33	u32 HcCommonStatus;
	34	u32 HcInterruptStatus;
	35	u32 HcInterruptEnable;
	36	u32 HcInterruptDisable;
	37	u32 HcHCCA;
	38	u32 HcPeriodCuttendED;
	39	u32 HcControlHeadED;
	40	u32 HcControlCurrentED;
	41	u32 HcBulkHeadED;
	42	u32 HcBuldCurrentED;
	43	u32 HcDoneHead;
	44	u32 HcRmInterval;
	45	u32 HcFmRemaining;
	46	u32 HcFmNumber;
	47	u32 HcPeriodicStart;
	48	u32 HcLSThreshold;
	49	u32 HcRhDescriptorA;
	50	u32 HcRhDescriptorB;
	51	u32 HcRhStatus;
	52	u32 HcRhPortStatus1;
	53	u32 HcRhPortStatus2;
8250d0ba	54	};
48b42616 WD	55
	56
	57	/* INTERRUPT (see manual chapter 14) */
8250d0ba	58	struct s3c24x0_interrupt {
d9abba82 N	59	u32 srcpnd;
	60	u32 intmod;
	61	u32 intmsk;
	62	u32 priority;
	63	u32 intpnd;
	64	u32 intoffset;
	65	#if defined(CONFIG_S3C2410) \|\| defined(CONFIG_S3C2440)
	66	u32 subsrcpnd;
	67	u32 intsubmsk;
48b42616	68	#endif
8250d0ba	69	};
48b42616 WD	70
	71
	72	/* DMAS (see manual chapter 8) */
8250d0ba	73	struct s3c24x0_dma {
d9abba82 N	74	u32 disrc;
	75	#if defined(CONFIG_S3C2410) \|\| defined(CONFIG_S3C2440)
	76	u32 disrcc;
48b42616	77	#endif
d9abba82 N	78	u32 didst;
	79	#if defined(CONFIG_S3C2410) \|\| defined(CONFIG_S3C2440)
	80	u32 didstc;
48b42616	81	#endif
d9abba82 N	82	u32 dcon;
	83	u32 dstat;
	84	u32 dcsrc;
	85	u32 dcdst;
	86	u32 dmasktrig;
	87	#if defined(CONFIG_S3C2400) \|\| defined(CONFIG_S3C2410) \
	88	\|\| defined(CONFIG_S3C2440)
9ebfdc20	89	u32 res[1];
48b42616	90	#endif
8250d0ba	91	};
48b42616	92
8250d0ba	93	struct s3c24x0_dmas {
	94	struct s3c24x0_dma dma[4];
	95	};
48b42616 WD	96
	97
	98	/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
	99	/* (see S3C2410 manual chapter 7) */
8250d0ba	100	struct s3c24x0_clock_power {
d9abba82 N	101	u32 locktime;
	102	u32 mpllcon;
	103	u32 upllcon;
	104	u32 clkcon;
	105	u32 clkslow;
	106	u32 clkdivn;
	107	#if defined(CONFIG_S3C2440)
	108	u32 camdivn;
	109	#endif
8250d0ba	110	};
48b42616 WD	111
	112
	113	/* LCD CONTROLLER (see manual chapter 15) */
8250d0ba	114	struct s3c24x0_lcd {
d9abba82 N	115	u32 lcdcon1;
	116	u32 lcdcon2;
	117	u32 lcdcon3;
	118	u32 lcdcon4;
	119	u32 lcdcon5;
	120	u32 lcdsaddr1;
	121	u32 lcdsaddr2;
	122	u32 lcdsaddr3;
	123	u32 redlut;
	124	u32 greenlut;
	125	u32 bluelut;
9ebfdc20	126	u32 res[8];
d9abba82 N	127	u32 dithmode;
	128	u32 tpal;
	129	#if defined(CONFIG_S3C2410) \|\| defined(CONFIG_S3C2440)
	130	u32 lcdintpnd;
	131	u32 lcdsrcpnd;
	132	u32 lcdintmsk;
	133	u32 lpcsel;
48b42616	134	#endif
8250d0ba	135	};
48b42616 WD	136
48b42616 WD	137
d9abba82	138	#ifdef CONFIG_S3C2410
48b42616	139	/* NAND FLASH (see S3C2410 manual chapter 6) */
8250d0ba	140	struct s3c2410_nand {
d9abba82 N	141	u32 nfconf;
	142	u32 nfcmd;
	143	u32 nfaddr;
	144	u32 nfdata;
	145	u32 nfstat;
	146	u32 nfecc;
	147	};
	148	#endif
	149	#ifdef CONFIG_S3C2440
	150	/* NAND FLASH (see S3C2440 manual chapter 6) */
	151	struct s3c2440_nand {
	152	u32 nfconf;
	153	u32 nfcont;
	154	u32 nfcmd;
	155	u32 nfaddr;
	156	u32 nfdata;
	157	u32 nfeccd0;
	158	u32 nfeccd1;
	159	u32 nfeccd;
	160	u32 nfstat;
	161	u32 nfstat0;
	162	u32 nfstat1;
8250d0ba	163	};
d9abba82	164	#endif
48b42616 WD	165
	166
	167	/* UART (see manual chapter 11) */
8250d0ba	168	struct s3c24x0_uart {
d9abba82 N	169	u32 ulcon;
	170	u32 ucon;
	171	u32 ufcon;
	172	u32 umcon;
	173	u32 utrstat;
	174	u32 uerstat;
	175	u32 ufstat;
	176	u32 umstat;
48b42616	177	#ifdef __BIG_ENDIAN
9ebfdc20	178	u8 res1[3];
d9abba82	179	u8 utxh;
9ebfdc20	180	u8 res2[3];
d9abba82	181	u8 urxh;
48b42616	182	#else /* Little Endian */
d9abba82	183	u8 utxh;
9ebfdc20	184	u8 res1[3];
d9abba82	185	u8 urxh;
9ebfdc20	186	u8 res2[3];
48b42616	187	#endif
d9abba82	188	u32 ubrdiv;
8250d0ba	189	};
48b42616 WD	190
	191
	192	/* PWM TIMER (see manual chapter 10) */
8250d0ba	193	struct s3c24x0_timer {
d9abba82 N	194	u32 tcntb;
	195	u32 tcmpb;
	196	u32 tcnto;
8250d0ba	197	};
48b42616	198
8250d0ba	199	struct s3c24x0_timers {
d9abba82 N	200	u32 tcfg0;
	201	u32 tcfg1;
	202	u32 tcon;
8250d0ba	203	struct s3c24x0_timer ch[4];
d9abba82 N	204	u32 tcntb4;
d9abba82 N	205	u32 tcnto4;
8250d0ba	206	};
48b42616 WD	207
	208
	209	/* USB DEVICE (see manual chapter 13) */
8250d0ba	210	struct s3c24x0_usb_dev_fifos {
48b42616	211	#ifdef __BIG_ENDIAN
9ebfdc20	212	u8 res[3];
d9abba82	213	u8 ep_fifo_reg;
48b42616	214	#else /* little endian */
d9abba82	215	u8 ep_fifo_reg;
9ebfdc20	216	u8 res[3];
48b42616	217	#endif
8250d0ba	218	};
48b42616	219
8250d0ba	220	struct s3c24x0_usb_dev_dmas {
48b42616	221	#ifdef __BIG_ENDIAN
9ebfdc20	222	u8 res1[3];
d9abba82	223	u8 ep_dma_con;
9ebfdc20	224	u8 res2[3];
d9abba82	225	u8 ep_dma_unit;
9ebfdc20	226	u8 res3[3];
d9abba82	227	u8 ep_dma_fifo;
9ebfdc20	228	u8 res4[3];
d9abba82	229	u8 ep_dma_ttc_l;
9ebfdc20	230	u8 res5[3];
d9abba82	231	u8 ep_dma_ttc_m;
9ebfdc20	232	u8 res6[3];
d9abba82	233	u8 ep_dma_ttc_h;
48b42616	234	#else /* little endian */
d9abba82	235	u8 ep_dma_con;
9ebfdc20	236	u8 res1[3];
d9abba82	237	u8 ep_dma_unit;
9ebfdc20	238	u8 res2[3];
d9abba82	239	u8 ep_dma_fifo;
9ebfdc20	240	u8 res3[3];
d9abba82	241	u8 ep_dma_ttc_l;
9ebfdc20	242	u8 res4[3];
d9abba82	243	u8 ep_dma_ttc_m;
9ebfdc20	244	u8 res5[3];
d9abba82	245	u8 ep_dma_ttc_h;
9ebfdc20	246	u8 res6[3];
48b42616	247	#endif
8250d0ba	248	};
48b42616	249
8250d0ba	250	struct s3c24x0_usb_device {
48b42616	251	#ifdef __BIG_ENDIAN
9ebfdc20	252	u8 res1[3];
d9abba82	253	u8 func_addr_reg;
9ebfdc20	254	u8 res2[3];
d9abba82	255	u8 pwr_reg;
9ebfdc20	256	u8 res3[3];
d9abba82	257	u8 ep_int_reg;
9ebfdc20	258	u8 res4[15];
d9abba82	259	u8 usb_int_reg;
9ebfdc20	260	u8 res5[3];
d9abba82	261	u8 ep_int_en_reg;
9ebfdc20	262	u8 res6[15];
d9abba82	263	u8 usb_int_en_reg;
9ebfdc20	264	u8 res7[3];
d9abba82	265	u8 frame_num1_reg;
9ebfdc20	266	u8 res8[3];
d9abba82	267	u8 frame_num2_reg;
9ebfdc20	268	u8 res9[3];
d9abba82	269	u8 index_reg;
9ebfdc20	270	u8 res10[7];
d9abba82	271	u8 maxp_reg;
9ebfdc20	272	u8 res11[3];
d9abba82	273	u8 ep0_csr_in_csr1_reg;
9ebfdc20	274	u8 res12[3];
d9abba82	275	u8 in_csr2_reg;
9ebfdc20	276	u8 res13[7];
d9abba82	277	u8 out_csr1_reg;
9ebfdc20	278	u8 res14[3];
d9abba82	279	u8 out_csr2_reg;
9ebfdc20	280	u8 res15[3];
d9abba82	281	u8 out_fifo_cnt1_reg;
9ebfdc20	282	u8 res16[3];
d9abba82	283	u8 out_fifo_cnt2_reg;
48b42616	284	#else /* little endian */
d9abba82	285	u8 func_addr_reg;
9ebfdc20	286	u8 res1[3];
d9abba82	287	u8 pwr_reg;
9ebfdc20	288	u8 res2[3];
d9abba82	289	u8 ep_int_reg;
9ebfdc20	290	u8 res3[15];
d9abba82	291	u8 usb_int_reg;
9ebfdc20	292	u8 res4[3];
d9abba82	293	u8 ep_int_en_reg;
9ebfdc20	294	u8 res5[15];
d9abba82	295	u8 usb_int_en_reg;
9ebfdc20	296	u8 res6[3];
d9abba82	297	u8 frame_num1_reg;
9ebfdc20	298	u8 res7[3];
d9abba82	299	u8 frame_num2_reg;
9ebfdc20	300	u8 res8[3];
d9abba82	301	u8 index_reg;
9ebfdc20	302	u8 res9[7];
d9abba82	303	u8 maxp_reg;
9ebfdc20	304	u8 res10[7];
d9abba82	305	u8 ep0_csr_in_csr1_reg;
9ebfdc20	306	u8 res11[3];
d9abba82	307	u8 in_csr2_reg;
9ebfdc20	308	u8 res12[3];
d9abba82	309	u8 out_csr1_reg;
9ebfdc20	310	u8 res13[7];
d9abba82	311	u8 out_csr2_reg;
9ebfdc20	312	u8 res14[3];
d9abba82	313	u8 out_fifo_cnt1_reg;
9ebfdc20	314	u8 res15[3];
d9abba82	315	u8 out_fifo_cnt2_reg;
9ebfdc20	316	u8 res16[3];
48b42616	317	#endif /* __BIG_ENDIAN */
8250d0ba	318	struct s3c24x0_usb_dev_fifos fifo[5];
	319	struct s3c24x0_usb_dev_dmas dma[5];
	320	};
48b42616 WD	321
	322
	323	/* WATCH DOG TIMER (see manual chapter 18) */
8250d0ba	324	struct s3c24x0_watchdog {
d9abba82 N	325	u32 wtcon;
	326	u32 wtdat;
	327	u32 wtcnt;
8250d0ba	328	};
48b42616	329
48b42616	330	/* IIS (see manual chapter 21) */
8250d0ba	331	struct s3c24x0_i2s {
48b42616	332	#ifdef __BIG_ENDIAN
9ebfdc20	333	u16 res1;
d9abba82	334	u16 iiscon;
9ebfdc20	335	u16 res2;
d9abba82	336	u16 iismod;
9ebfdc20	337	u16 res3;
d9abba82	338	u16 iispsr;
9ebfdc20	339	u16 res4;
d9abba82	340	u16 iisfcon;
9ebfdc20	341	u16 res5;
d9abba82	342	u16 iisfifo;
48b42616	343	#else /* little endian */
d9abba82	344	u16 iiscon;
9ebfdc20	345	u16 res1;
d9abba82	346	u16 iismod;
9ebfdc20	347	u16 res2;
d9abba82	348	u16 iispsr;
9ebfdc20	349	u16 res3;
d9abba82	350	u16 iisfcon;
9ebfdc20	351	u16 res4;
d9abba82	352	u16 iisfifo;
9ebfdc20	353	u16 res5;
48b42616	354	#endif
8250d0ba	355	};
48b42616 WD	356
	357
	358	/* I/O PORT (see manual chapter 9) */
8250d0ba	359	struct s3c24x0_gpio {
48b42616	360	#ifdef CONFIG_S3C2400
d9abba82 N	361	u32 pacon;
d9abba82 N	362	u32 padat;
8bde7f77	363
d9abba82 N	364	u32 pbcon;
	365	u32 pbdat;
	366	u32 pbup;
48b42616	367
d9abba82 N	368	u32 pccon;
	369	u32 pcdat;
	370	u32 pcup;
48b42616	371
d9abba82 N	372	u32 pdcon;
	373	u32 pddat;
	374	u32 pdup;
48b42616	375
d9abba82 N	376	u32 pecon;
	377	u32 pedat;
	378	u32 peup;
48b42616	379
d9abba82 N	380	u32 pfcon;
	381	u32 pfdat;
	382	u32 pfup;
48b42616	383
d9abba82 N	384	u32 pgcon;
	385	u32 pgdat;
	386	u32 pgup;
48b42616	387
d9abba82	388	u32 opencr;
48b42616	389
d9abba82 N	390	u32 misccr;
d9abba82 N	391	u32 extint;
48b42616 WD	392	#endif
48b42616 WD	393	#ifdef CONFIG_S3C2410
d9abba82 N	394	u32 gpacon;
	395	u32 gpadat;
	396	u32 res1[2];
	397	u32 gpbcon;
	398	u32 gpbdat;
	399	u32 gpbup;
	400	u32 res2;
	401	u32 gpccon;
	402	u32 gpcdat;
	403	u32 gpcup;
	404	u32 res3;
	405	u32 gpdcon;
	406	u32 gpddat;
	407	u32 gpdup;
	408	u32 res4;
	409	u32 gpecon;
	410	u32 gpedat;
	411	u32 gpeup;
	412	u32 res5;
	413	u32 gpfcon;
	414	u32 gpfdat;
	415	u32 gpfup;
	416	u32 res6;
	417	u32 gpgcon;
	418	u32 gpgdat;
	419	u32 gpgup;
	420	u32 res7;
	421	u32 gphcon;
	422	u32 gphdat;
	423	u32 gphup;
	424	u32 res8;
	425
	426	u32 misccr;
	427	u32 dclkcon;
	428	u32 extint0;
	429	u32 extint1;
	430	u32 extint2;
	431	u32 eintflt0;
	432	u32 eintflt1;
	433	u32 eintflt2;
	434	u32 eintflt3;
	435	u32 eintmask;
	436	u32 eintpend;
	437	u32 gstatus0;
	438	u32 gstatus1;
	439	u32 gstatus2;
	440	u32 gstatus3;
	441	u32 gstatus4;
	442	#endif
	443	#if defined(CONFIG_S3C2440)
	444	u32 gpacon;
	445	u32 gpadat;
9ebfdc20	446	u32 res1[2];
d9abba82 N	447	u32 gpbcon;
	448	u32 gpbdat;
	449	u32 gpbup;
9ebfdc20	450	u32 res2;
d9abba82 N	451	u32 gpccon;
	452	u32 gpcdat;
	453	u32 gpcup;
9ebfdc20	454	u32 res3;
d9abba82 N	455	u32 gpdcon;
	456	u32 gpddat;
	457	u32 gpdup;
9ebfdc20	458	u32 res4;
d9abba82 N	459	u32 gpecon;
	460	u32 gpedat;
	461	u32 gpeup;
9ebfdc20	462	u32 res5;
d9abba82 N	463	u32 gpfcon;
	464	u32 gpfdat;
	465	u32 gpfup;
9ebfdc20	466	u32 res6;
d9abba82 N	467	u32 gpgcon;
	468	u32 gpgdat;
	469	u32 gpgup;
9ebfdc20	470	u32 res7;
d9abba82 N	471	u32 gphcon;
	472	u32 gphdat;
	473	u32 gphup;
9ebfdc20	474	u32 res8;
9ebfdc20	475
d9abba82 N	476	u32 misccr;
	477	u32 dclkcon;
	478	u32 extint0;
	479	u32 extint1;
	480	u32 extint2;
	481	u32 eintflt0;
	482	u32 eintflt1;
	483	u32 eintflt2;
	484	u32 eintflt3;
	485	u32 eintmask;
	486	u32 eintpend;
	487	u32 gstatus0;
	488	u32 gstatus1;
	489	u32 gstatus2;
	490	u32 gstatus3;
	491	u32 gstatus4;
	492
	493	u32 res9;
	494	u32 dsc0;
	495	u32 dsc1;
	496	u32 mslcon;
	497	u32 gpjcon;
	498	u32 gpjdat;
	499	u32 gpjup;
	500	u32 res10;
48b42616	501	#endif
8250d0ba	502	};
48b42616 WD	503
	504
	505	/* RTC (see manual chapter 17) */
8250d0ba	506	struct s3c24x0_rtc {
48b42616	507	#ifdef __BIG_ENDIAN
9ebfdc20	508	u8 res1[67];
d9abba82	509	u8 rtccon;
9ebfdc20	510	u8 res2[3];
d9abba82	511	u8 ticnt;
9ebfdc20	512	u8 res3[11];
d9abba82	513	u8 rtcalm;
9ebfdc20	514	u8 res4[3];
d9abba82	515	u8 almsec;
9ebfdc20	516	u8 res5[3];
d9abba82	517	u8 almmin;
9ebfdc20	518	u8 res6[3];
d9abba82	519	u8 almhour;
9ebfdc20	520	u8 res7[3];
d9abba82	521	u8 almdate;
9ebfdc20	522	u8 res8[3];
d9abba82	523	u8 almmon;
9ebfdc20	524	u8 res9[3];
d9abba82	525	u8 almyear;
9ebfdc20	526	u8 res10[3];
d9abba82	527	u8 rtcrst;
9ebfdc20	528	u8 res11[3];
d9abba82	529	u8 bcdsec;
9ebfdc20	530	u8 res12[3];
d9abba82	531	u8 bcdmin;
9ebfdc20	532	u8 res13[3];
d9abba82	533	u8 bcdhour;
9ebfdc20	534	u8 res14[3];
d9abba82	535	u8 bcddate;
9ebfdc20	536	u8 res15[3];
d9abba82	537	u8 bcdday;
9ebfdc20	538	u8 res16[3];
d9abba82	539	u8 bcdmon;
9ebfdc20	540	u8 res17[3];
d9abba82	541	u8 bcdyear;
48b42616	542	#else /* little endian */
9ebfdc20	543	u8 res0[64];
d9abba82	544	u8 rtccon;
9ebfdc20	545	u8 res1[3];
d9abba82	546	u8 ticnt;
9ebfdc20	547	u8 res2[11];
d9abba82	548	u8 rtcalm;
9ebfdc20	549	u8 res3[3];
d9abba82	550	u8 almsec;
9ebfdc20	551	u8 res4[3];
d9abba82	552	u8 almmin;
9ebfdc20	553	u8 res5[3];
d9abba82	554	u8 almhour;
9ebfdc20	555	u8 res6[3];
d9abba82	556	u8 almdate;
9ebfdc20	557	u8 res7[3];
d9abba82	558	u8 almmon;
9ebfdc20	559	u8 res8[3];
d9abba82	560	u8 almyear;
9ebfdc20	561	u8 res9[3];
d9abba82	562	u8 rtcrst;
9ebfdc20	563	u8 res10[3];
d9abba82	564	u8 bcdsec;
9ebfdc20	565	u8 res11[3];
d9abba82	566	u8 bcdmin;
9ebfdc20	567	u8 res12[3];
d9abba82	568	u8 bcdhour;
9ebfdc20	569	u8 res13[3];
d9abba82	570	u8 bcddate;
9ebfdc20	571	u8 res14[3];
d9abba82	572	u8 bcdday;
9ebfdc20	573	u8 res15[3];
d9abba82	574	u8 bcdmon;
9ebfdc20	575	u8 res16[3];
d9abba82	576	u8 bcdyear;
9ebfdc20	577	u8 res17[3];
48b42616	578	#endif
8250d0ba	579	};
48b42616 WD	580
	581
	582	/* ADC (see manual chapter 16) */
8250d0ba	583	struct s3c2400_adc {
d9abba82 N	584	u32 adccon;
d9abba82 N	585	u32 adcdat;
8250d0ba	586	};
48b42616 WD	587
	588
	589	/* ADC (see manual chapter 16) */
8250d0ba	590	struct s3c2410_adc {
d9abba82 N	591	u32 adccon;
	592	u32 adctsc;
	593	u32 adcdly;
	594	u32 adcdat0;
	595	u32 adcdat1;
8250d0ba	596	};
48b42616 WD	597
	598
	599	/* SPI (see manual chapter 22) */
8250d0ba	600	struct s3c24x0_spi_channel {
d9abba82	601	u8 spcon;
9ebfdc20	602	u8 res1[3];
d9abba82	603	u8 spsta;
9ebfdc20	604	u8 res2[3];
d9abba82	605	u8 sppin;
9ebfdc20	606	u8 res3[3];
d9abba82	607	u8 sppre;
9ebfdc20	608	u8 res4[3];
d9abba82	609	u8 sptdat;
9ebfdc20	610	u8 res5[3];
d9abba82	611	u8 sprdat;
9ebfdc20	612	u8 res6[3];
9ebfdc20	613	u8 res7[16];
8250d0ba	614	};
48b42616	615
8250d0ba	616	struct s3c24x0_spi {
	617	struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
	618	};
48b42616 WD	619
	620
	621	/* MMC INTERFACE (see S3C2400 manual chapter 19) */
8250d0ba	622	struct s3c2400_mmc {
48b42616	623	#ifdef __BIG_ENDIAN
9ebfdc20	624	u8 res1[3];
d9abba82	625	u8 mmcon;
9ebfdc20	626	u8 res2[3];
d9abba82	627	u8 mmcrr;
9ebfdc20	628	u8 res3[3];
d9abba82	629	u8 mmfcon;
9ebfdc20	630	u8 res4[3];
d9abba82	631	u8 mmsta;
9ebfdc20	632	u16 res5;
d9abba82	633	u16 mmfsta;
9ebfdc20	634	u8 res6[3];
d9abba82	635	u8 mmpre;
9ebfdc20	636	u16 res7;
d9abba82	637	u16 mmlen;
9ebfdc20	638	u8 res8[3];
d9abba82 N	639	u8 mmcr7;
d9abba82 N	640	u32 mmrsp[4];
9ebfdc20	641	u8 res9[3];
d9abba82 N	642	u8 mmcmd0;
d9abba82 N	643	u32 mmcmd1;
9ebfdc20	644	u16 res10;
d9abba82	645	u16 mmcr16;
9ebfdc20	646	u8 res11[3];
d9abba82	647	u8 mmdat;
48b42616	648	#else
d9abba82	649	u8 mmcon;
9ebfdc20	650	u8 res1[3];
d9abba82	651	u8 mmcrr;
9ebfdc20	652	u8 res2[3];
d9abba82	653	u8 mmfcon;
9ebfdc20	654	u8 res3[3];
d9abba82	655	u8 mmsta;
9ebfdc20	656	u8 res4[3];
d9abba82	657	u16 mmfsta;
9ebfdc20	658	u16 res5;
d9abba82	659	u8 mmpre;
9ebfdc20	660	u8 res6[3];
d9abba82	661	u16 mmlen;
9ebfdc20	662	u16 res7;
d9abba82	663	u8 mmcr7;
9ebfdc20	664	u8 res8[3];
d9abba82 N	665	u32 mmrsp[4];
d9abba82 N	666	u8 mmcmd0;
9ebfdc20	667	u8 res9[3];
d9abba82 N	668	u32 mmcmd1;
d9abba82 N	669	u16 mmcr16;
9ebfdc20	670	u16 res10;
d9abba82	671	u8 mmdat;
9ebfdc20	672	u8 res11[3];
48b42616	673	#endif
8250d0ba	674	};
48b42616 WD	675
	676
	677	/* SD INTERFACE (see S3C2410 manual chapter 19) */
8250d0ba	678	struct s3c2410_sdi {
d9abba82 N	679	u32 sdicon;
	680	u32 sdipre;
	681	u32 sdicarg;
	682	u32 sdiccon;
	683	u32 sdicsta;
	684	u32 sdirsp0;
	685	u32 sdirsp1;
	686	u32 sdirsp2;
	687	u32 sdirsp3;
	688	u32 sdidtimer;
	689	u32 sdibsize;
	690	u32 sdidcon;
	691	u32 sdidcnt;
	692	u32 sdidsta;
	693	u32 sdifsta;
48b42616	694	#ifdef __BIG_ENDIAN
9ebfdc20	695	u8 res[3];
d9abba82	696	u8 sdidat;
48b42616	697	#else
d9abba82	698	u8 sdidat;
9ebfdc20	699	u8 res[3];
48b42616	700	#endif
d9abba82	701	u32 sdiimsk;
8250d0ba	702	};
48b42616 WD	703
48b42616 WD	704	#endif /__S3C24X0_H__/