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ARM: tegra: support running in non-secure mode
[people/ms/u-boot.git] / arch / arm / include / asm / arch-tegra / ap.h
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1/*
2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7#include <asm/types.h>
8
9/* Stabilization delays, in usec */
b2871037 10#define PLL_STABILIZATION_DELAY (300)
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11#define IO_STABILIZATION_DELAY (1000)
12
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13#define PLLX_ENABLED (1 << 30)
14#define CCLK_BURST_POLICY 0x20008888
15#define SUPER_CCLK_DIVIDER 0x80000000
16
17/* Calculate clock fractional divider value from ref and target frequencies */
b2871037 18#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
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19
20/* Calculate clock frequency value from reference and clock divider value */
b2871037 21#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
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22
23/* AVP/CPU ID */
24#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
b2871037 25#define PG_UP_TAG_0 0x0
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26
27#define CORESIGHT_UNLOCK 0xC5ACCE55;
28
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29/* AP base physical address of internal SRAM */
30#define NV_PA_BASE_SRAM 0x40000000
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31
32#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
33#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
34#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
35
36#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
37#define FLOW_MODE_STOP 2
38#define HALT_COP_EVENT_JTAG (1 << 28)
39#define HALT_COP_EVENT_IRQ_1 (1 << 11)
40#define HALT_COP_EVENT_FIQ_1 (1 << 9)
41
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42/* This is the main entry into U-Boot, used by the Cortex-A9 */
43extern void _start(void);
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44
45/**
49493cb7 46 * Works out the SOC/SKU type used for clocks settings
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47 *
48 * @return SOC type - see TEGRA_SOC...
49 */
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50int tegra_get_chip_sku(void);
51
52/**
53 * Returns the pure SOC (chip ID) from the HIDREV register
54 *
55 * @return SOC ID - see CHIPID_TEGRAxx...
56 */
57int tegra_get_chip(void);
58
59/**
60 * Returns the SKU ID from the sku_info register
61 *
62 * @return SKU ID - see SKU_ID_Txx...
63 */
64int tegra_get_sku_info(void);
65
66/* Do any chip-specific cache config */
d0edce4f 67void config_cache(void);
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68
69#if defined(CONFIG_TEGRA124)
70/* Do chip-specific vpr config */
71void config_vpr(void);
72#else
73static inline void config_vpr(void)
74{
75}
76#endif
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77
78#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
79bool tegra_cpu_is_non_secure(void);
80#endif