[people/ms/u-boot.git] / arch / arm / include / asm / arch-tegra30 / clock-tables.h

/*
 * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

/* Tegra30 clock PLL tables */

#ifndef _TEGRA30_CLOCK_TABLES_H_
#define _TEGRA30_CLOCK_TABLES_H_

/* The PLLs supported by the hardware */
enum clock_id {
	CLOCK_ID_FIRST,
	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
	CLOCK_ID_MEMORY,
	CLOCK_ID_PERIPH,
	CLOCK_ID_AUDIO,
	CLOCK_ID_USB,
	CLOCK_ID_DISPLAY,

	/* now the simple ones */
	CLOCK_ID_FIRST_SIMPLE,
	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
	CLOCK_ID_EPCI,
	CLOCK_ID_SFROM32KHZ,

	/* These are the base clocks (inputs to the Tegra SOC) */
	CLOCK_ID_32KHZ,
	CLOCK_ID_OSC,
	CLOCK_ID_CLK_M,

	CLOCK_ID_COUNT,	/* number of PLLs */
	CLOCK_ID_DISPLAY2,	/* Tegra3, placeholder */
	CLOCK_ID_NONE = -1,
};

/* The clocks supported by the hardware */
enum periph_id {
	PERIPH_ID_FIRST,

	/* Low word: 31:0 */
	PERIPH_ID_CPU = PERIPH_ID_FIRST,
	PERIPH_ID_COP,
	PERIPH_ID_TRIGSYS,
	PERIPH_ID_RESERVED3,
	PERIPH_ID_RESERVED4,
	PERIPH_ID_TMR,
	PERIPH_ID_UART1,
	PERIPH_ID_UART2,

	/* 8 */
	PERIPH_ID_GPIO,
	PERIPH_ID_SDMMC2,
	PERIPH_ID_SPDIF,
	PERIPH_ID_I2S1,
	PERIPH_ID_I2C1,
	PERIPH_ID_NDFLASH,
	PERIPH_ID_SDMMC1,
	PERIPH_ID_SDMMC4,

	/* 16 */
	PERIPH_ID_RESERVED16,
	PERIPH_ID_PWM,
	PERIPH_ID_I2S2,
	PERIPH_ID_EPP,
	PERIPH_ID_VI,
	PERIPH_ID_2D,
	PERIPH_ID_USBD,
	PERIPH_ID_ISP,

	/* 24 */
	PERIPH_ID_3D,
	PERIPH_ID_RESERVED24,
	PERIPH_ID_DISP2,
	PERIPH_ID_DISP1,
	PERIPH_ID_HOST1X,
	PERIPH_ID_VCP,
	PERIPH_ID_I2S0,
	PERIPH_ID_CACHE2,

	/* Middle word: 63:32 */
	PERIPH_ID_MEM,
	PERIPH_ID_AHBDMA,
	PERIPH_ID_APBDMA,
	PERIPH_ID_RESERVED35,
	PERIPH_ID_KBC,
	PERIPH_ID_STAT_MON,
	PERIPH_ID_PMC,
	PERIPH_ID_FUSE,

	/* 40 */
	PERIPH_ID_KFUSE,
	PERIPH_ID_SBC1,
	PERIPH_ID_SNOR,
	PERIPH_ID_RESERVED43,
	PERIPH_ID_SBC2,
	PERIPH_ID_RESERVED45,
	PERIPH_ID_SBC3,
	PERIPH_ID_DVC_I2C,

	/* 48 */
	PERIPH_ID_DSI,
	PERIPH_ID_TVO,
	PERIPH_ID_MIPI,
	PERIPH_ID_HDMI,
	PERIPH_ID_CSI,
	PERIPH_ID_TVDAC,
	PERIPH_ID_I2C2,
	PERIPH_ID_UART3,

	/* 56 */
	PERIPH_ID_RESERVED56,
	PERIPH_ID_EMC,
	PERIPH_ID_USB2,
	PERIPH_ID_USB3,
	PERIPH_ID_MPE,
	PERIPH_ID_VDE,
	PERIPH_ID_BSEA,
	PERIPH_ID_BSEV,

	/* Upper word 95:64 */
	PERIPH_ID_SPEEDO,
	PERIPH_ID_UART4,
	PERIPH_ID_UART5,
	PERIPH_ID_I2C3,
	PERIPH_ID_SBC4,
	PERIPH_ID_SDMMC3,
	PERIPH_ID_PCIE,
	PERIPH_ID_OWR,

	/* 72 */
	PERIPH_ID_AFI,
	PERIPH_ID_CORESIGHT,
	PERIPH_ID_PCIEXCLK,
	PERIPH_ID_AVPUCQ,
	PERIPH_ID_RESERVED76,
	PERIPH_ID_RESERVED77,
	PERIPH_ID_RESERVED78,
	PERIPH_ID_DTV,

	/* 80 */
	PERIPH_ID_NANDSPEED,
	PERIPH_ID_I2CSLOW,
	PERIPH_ID_DSIB,
	PERIPH_ID_RESERVED83,
	PERIPH_ID_IRAMA,
	PERIPH_ID_IRAMB,
	PERIPH_ID_IRAMC,
	PERIPH_ID_IRAMD,

	/* 88 */
	PERIPH_ID_CRAM2,
	PERIPH_ID_RESERVED89,
	PERIPH_ID_MDOUBLER,
	PERIPH_ID_RESERVED91,
	PERIPH_ID_SUSOUT,
	PERIPH_ID_RESERVED93,
	PERIPH_ID_RESERVED94,
	PERIPH_ID_RESERVED95,

	PERIPH_ID_VW_FIRST,
	/* V word: 31:0 */
	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
	PERIPH_ID_CPULP,
	PERIPH_ID_3D2,
	PERIPH_ID_MSELECT,
	PERIPH_ID_TSENSOR,
	PERIPH_ID_I2S3,
	PERIPH_ID_I2S4,
	PERIPH_ID_I2C4,

	/* 08 */
	PERIPH_ID_SBC5,
	PERIPH_ID_SBC6,
	PERIPH_ID_AUDIO,
	PERIPH_ID_APBIF,
	PERIPH_ID_DAM0,
	PERIPH_ID_DAM1,
	PERIPH_ID_DAM2,
	PERIPH_ID_HDA2CODEC2X,

	/* 16 */
	PERIPH_ID_ATOMICS,
	PERIPH_ID_EX_RESERVED17,
	PERIPH_ID_EX_RESERVED18,
	PERIPH_ID_EX_RESERVED19,
	PERIPH_ID_EX_RESERVED20,
	PERIPH_ID_EX_RESERVED21,
	PERIPH_ID_EX_RESERVED22,
	PERIPH_ID_ACTMON,

	/* 24 */
	PERIPH_ID_EX_RESERVED24,
	PERIPH_ID_EX_RESERVED25,
	PERIPH_ID_EX_RESERVED26,
	PERIPH_ID_EX_RESERVED27,
	PERIPH_ID_SATA,
	PERIPH_ID_HDA,
	PERIPH_ID_EX_RESERVED30,
	PERIPH_ID_EX_RESERVED31,

	/* W word: 31:0 */
	PERIPH_ID_HDA2HDMICODEC,
	PERIPH_ID_SATACOLD,
	PERIPH_ID_RESERVED0_PCIERX0,
	PERIPH_ID_RESERVED1_PCIERX1,
	PERIPH_ID_RESERVED2_PCIERX2,
	PERIPH_ID_RESERVED3_PCIERX3,
	PERIPH_ID_RESERVED4_PCIERX4,
	PERIPH_ID_RESERVED5_PCIERX5,

	/* 40 */
	PERIPH_ID_CEC,
	PERIPH_ID_RESERVED6_PCIE2,
	PERIPH_ID_RESERVED7_EMC,
	PERIPH_ID_RESERVED8_HDMI,
	PERIPH_ID_RESERVED9_SATA,
	PERIPH_ID_RESERVED10_MIPI,
	PERIPH_ID_EX_RESERVED46,
	PERIPH_ID_EX_RESERVED47,

	PERIPH_ID_COUNT,
	PERIPH_ID_NONE = -1,
};

enum pll_out_id {
	PLL_OUT1,
	PLL_OUT2,
	PLL_OUT3,
	PLL_OUT4
};

/*
 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
 * confusion bewteen PERIPH_ID_... and PERIPHC_...
 *
 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
 * confusing.
 */
enum periphc_internal_id {
	/* 0x00 */
	PERIPHC_I2S1,
	PERIPHC_I2S2,
	PERIPHC_SPDIF_OUT,
	PERIPHC_SPDIF_IN,
	PERIPHC_PWM,
	PERIPHC_05h,
	PERIPHC_SBC2,
	PERIPHC_SBC3,

	/* 0x08 */
	PERIPHC_08h,
	PERIPHC_I2C1,
	PERIPHC_DVC_I2C,
	PERIPHC_0bh,
	PERIPHC_0ch,
	PERIPHC_SBC1,
	PERIPHC_DISP1,
	PERIPHC_DISP2,

	/* 0x10 */
	PERIPHC_CVE,
	PERIPHC_11h,
	PERIPHC_VI,
	PERIPHC_13h,
	PERIPHC_SDMMC1,
	PERIPHC_SDMMC2,
	PERIPHC_G3D,
	PERIPHC_G2D,

	/* 0x18 */
	PERIPHC_NDFLASH,
	PERIPHC_SDMMC4,
	PERIPHC_VFIR,
	PERIPHC_EPP,
	PERIPHC_MPE,
	PERIPHC_MIPI,
	PERIPHC_UART1,
	PERIPHC_UART2,

	/* 0x20 */
	PERIPHC_HOST1X,
	PERIPHC_21h,
	PERIPHC_TVO,
	PERIPHC_HDMI,
	PERIPHC_24h,
	PERIPHC_TVDAC,
	PERIPHC_I2C2,
	PERIPHC_EMC,

	/* 0x28 */
	PERIPHC_UART3,
	PERIPHC_29h,
	PERIPHC_VI_SENSOR,
	PERIPHC_2bh,
	PERIPHC_2ch,
	PERIPHC_SBC4,
	PERIPHC_I2C3,
	PERIPHC_SDMMC3,

	/* 0x30 */
	PERIPHC_UART4,
	PERIPHC_UART5,
	PERIPHC_VDE,
	PERIPHC_OWR,
	PERIPHC_NOR,
	PERIPHC_CSITE,
	PERIPHC_I2S0,
	PERIPHC_37h,

	PERIPHC_VW_FIRST,
	/* 0x38 */
	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
	PERIPHC_MSELECT,
	PERIPHC_TSENSOR,
	PERIPHC_I2S3,
	PERIPHC_I2S4,
	PERIPHC_I2C4,
	PERIPHC_SBC5,
	PERIPHC_SBC6,

	/* 0x40 */
	PERIPHC_AUDIO,
	PERIPHC_41h,
	PERIPHC_DAM0,
	PERIPHC_DAM1,
	PERIPHC_DAM2,
	PERIPHC_HDA2CODEC2X,
	PERIPHC_ACTMON,
	PERIPHC_EXTPERIPH1,

	/* 0x48 */
	PERIPHC_EXTPERIPH2,
	PERIPHC_EXTPERIPH3,
	PERIPHC_NANDSPEED,
	PERIPHC_I2CSLOW,
	PERIPHC_SYS,
	PERIPHC_SPEEDO,
	PERIPHC_4eh,
	PERIPHC_4fh,

	/* 0x50 */
	PERIPHC_50h,
	PERIPHC_51h,
	PERIPHC_52h,
	PERIPHC_53h,
	PERIPHC_SATAOOB,
	PERIPHC_SATA,
	PERIPHC_HDA,

	PERIPHC_COUNT,

	PERIPHC_NONE = -1,
};

/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
#define PERIPH_REG(id) \
	(id < PERIPH_ID_VW_FIRST) ? \
		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)

/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))

/* return 1 if a PLL ID is in range */
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)

/* return 1 if a peripheral ID is in range */
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
		(id) < PERIPH_ID_COUNT)

#endif	/* _TEGRA30_CLOCK_TABLES_H_ */
Commit	Line	Data
dc89ad14 TW	1	/*
	2	* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
	3	*
5b8031cc	4	* SPDX-License-Identifier: GPL-2.0
dc89ad14 TW	5	*/
	6
	7	/* Tegra30 clock PLL tables */
	8
	9	#ifndef _TEGRA30_CLOCK_TABLES_H_
	10	#define _TEGRA30_CLOCK_TABLES_H_
	11
	12	/* The PLLs supported by the hardware */
	13	enum clock_id {
	14	CLOCK_ID_FIRST,
	15	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
	16	CLOCK_ID_MEMORY,
	17	CLOCK_ID_PERIPH,
	18	CLOCK_ID_AUDIO,
	19	CLOCK_ID_USB,
	20	CLOCK_ID_DISPLAY,
	21
	22	/* now the simple ones */
	23	CLOCK_ID_FIRST_SIMPLE,
	24	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
	25	CLOCK_ID_EPCI,
	26	CLOCK_ID_SFROM32KHZ,
	27
	28	/* These are the base clocks (inputs to the Tegra SOC) */
	29	CLOCK_ID_32KHZ,
	30	CLOCK_ID_OSC,
c043c025	31	CLOCK_ID_CLK_M,
dc89ad14 TW	32
	33	CLOCK_ID_COUNT, /* number of PLLs */
	34	CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
	35	CLOCK_ID_NONE = -1,
	36	};
	37
	38	/* The clocks supported by the hardware */
	39	enum periph_id {
	40	PERIPH_ID_FIRST,
	41
	42	/* Low word: 31:0 */
	43	PERIPH_ID_CPU = PERIPH_ID_FIRST,
	44	PERIPH_ID_COP,
	45	PERIPH_ID_TRIGSYS,
	46	PERIPH_ID_RESERVED3,
	47	PERIPH_ID_RESERVED4,
	48	PERIPH_ID_TMR,
	49	PERIPH_ID_UART1,
	50	PERIPH_ID_UART2,
	51
	52	/* 8 */
	53	PERIPH_ID_GPIO,
	54	PERIPH_ID_SDMMC2,
	55	PERIPH_ID_SPDIF,
	56	PERIPH_ID_I2S1,
	57	PERIPH_ID_I2C1,
	58	PERIPH_ID_NDFLASH,
	59	PERIPH_ID_SDMMC1,
	60	PERIPH_ID_SDMMC4,
	61
	62	/* 16 */
	63	PERIPH_ID_RESERVED16,
	64	PERIPH_ID_PWM,
	65	PERIPH_ID_I2S2,
	66	PERIPH_ID_EPP,
	67	PERIPH_ID_VI,
	68	PERIPH_ID_2D,
	69	PERIPH_ID_USBD,
	70	PERIPH_ID_ISP,
	71
	72	/* 24 */
	73	PERIPH_ID_3D,
	74	PERIPH_ID_RESERVED24,
	75	PERIPH_ID_DISP2,
	76	PERIPH_ID_DISP1,
	77	PERIPH_ID_HOST1X,
	78	PERIPH_ID_VCP,
	79	PERIPH_ID_I2S0,
	80	PERIPH_ID_CACHE2,
	81
	82	/* Middle word: 63:32 */
	83	PERIPH_ID_MEM,
	84	PERIPH_ID_AHBDMA,
	85	PERIPH_ID_APBDMA,
	86	PERIPH_ID_RESERVED35,
	87	PERIPH_ID_KBC,
	88	PERIPH_ID_STAT_MON,
	89	PERIPH_ID_PMC,
	90	PERIPH_ID_FUSE,
	91
	92	/* 40 */
	93	PERIPH_ID_KFUSE,
	94	PERIPH_ID_SBC1,
	95	PERIPH_ID_SNOR,
96	PERIPH_ID_RESERVED43,
97	PERIPH_ID_SBC2,
98	PERIPH_ID_RESERVED45,
99	PERIPH_ID_SBC3,
100	PERIPH_ID_DVC_I2C,
101
102	/* 48 */
103	PERIPH_ID_DSI,
104	PERIPH_ID_TVO,
105	PERIPH_ID_MIPI,
106	PERIPH_ID_HDMI,
107	PERIPH_ID_CSI,
108	PERIPH_ID_TVDAC,
109	PERIPH_ID_I2C2,
110	PERIPH_ID_UART3,
111
112	/* 56 */
113	PERIPH_ID_RESERVED56,
114	PERIPH_ID_EMC,
115	PERIPH_ID_USB2,
116	PERIPH_ID_USB3,
117	PERIPH_ID_MPE,
118	PERIPH_ID_VDE,
119	PERIPH_ID_BSEA,
120	PERIPH_ID_BSEV,
121
122	/* Upper word 95:64 */
123	PERIPH_ID_SPEEDO,
124	PERIPH_ID_UART4,
125	PERIPH_ID_UART5,
126	PERIPH_ID_I2C3,
127	PERIPH_ID_SBC4,
128	PERIPH_ID_SDMMC3,
129	PERIPH_ID_PCIE,
130	PERIPH_ID_OWR,
131
132	/* 72 */
133	PERIPH_ID_AFI,
134	PERIPH_ID_CORESIGHT,
135	PERIPH_ID_PCIEXCLK,
136	PERIPH_ID_AVPUCQ,
137	PERIPH_ID_RESERVED76,
138	PERIPH_ID_RESERVED77,
139	PERIPH_ID_RESERVED78,
140	PERIPH_ID_DTV,
141
142	/* 80 */
143	PERIPH_ID_NANDSPEED,
144	PERIPH_ID_I2CSLOW,
145	PERIPH_ID_DSIB,
146	PERIPH_ID_RESERVED83,
147	PERIPH_ID_IRAMA,
148	PERIPH_ID_IRAMB,
149	PERIPH_ID_IRAMC,
150	PERIPH_ID_IRAMD,
151
152	/* 88 */
153	PERIPH_ID_CRAM2,
154	PERIPH_ID_RESERVED89,
155	PERIPH_ID_MDOUBLER,
156	PERIPH_ID_RESERVED91,
157	PERIPH_ID_SUSOUT,
158	PERIPH_ID_RESERVED93,
159	PERIPH_ID_RESERVED94,
160	PERIPH_ID_RESERVED95,
161
162	PERIPH_ID_VW_FIRST,
163	/* V word: 31:0 */
164	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
165	PERIPH_ID_CPULP,
166	PERIPH_ID_3D2,
167	PERIPH_ID_MSELECT,
168	PERIPH_ID_TSENSOR,
169	PERIPH_ID_I2S3,
170	PERIPH_ID_I2S4,
171	PERIPH_ID_I2C4,
172
173	/* 08 */
174	PERIPH_ID_SBC5,
175	PERIPH_ID_SBC6,
176	PERIPH_ID_AUDIO,
177	PERIPH_ID_APBIF,
178	PERIPH_ID_DAM0,
179	PERIPH_ID_DAM1,
180	PERIPH_ID_DAM2,
181	PERIPH_ID_HDA2CODEC2X,
182
183	/* 16 */
184	PERIPH_ID_ATOMICS,
185	PERIPH_ID_EX_RESERVED17,
186	PERIPH_ID_EX_RESERVED18,
187	PERIPH_ID_EX_RESERVED19,
188	PERIPH_ID_EX_RESERVED20,
189	PERIPH_ID_EX_RESERVED21,
190	PERIPH_ID_EX_RESERVED22,
191	PERIPH_ID_ACTMON,
192
193	/* 24 */
194	PERIPH_ID_EX_RESERVED24,
195	PERIPH_ID_EX_RESERVED25,
196	PERIPH_ID_EX_RESERVED26,
197	PERIPH_ID_EX_RESERVED27,
198	PERIPH_ID_SATA,
199	PERIPH_ID_HDA,
200	PERIPH_ID_EX_RESERVED30,
201	PERIPH_ID_EX_RESERVED31,
202
203	/* W word: 31:0 */
204	PERIPH_ID_HDA2HDMICODEC,
205	PERIPH_ID_SATACOLD,
206	PERIPH_ID_RESERVED0_PCIERX0,
207	PERIPH_ID_RESERVED1_PCIERX1,
208	PERIPH_ID_RESERVED2_PCIERX2,
209	PERIPH_ID_RESERVED3_PCIERX3,
210	PERIPH_ID_RESERVED4_PCIERX4,
211	PERIPH_ID_RESERVED5_PCIERX5,
212
213	/* 40 */
214	PERIPH_ID_CEC,
215	PERIPH_ID_RESERVED6_PCIE2,
216	PERIPH_ID_RESERVED7_EMC,
217	PERIPH_ID_RESERVED8_HDMI,
218	PERIPH_ID_RESERVED9_SATA,
219	PERIPH_ID_RESERVED10_MIPI,
220	PERIPH_ID_EX_RESERVED46,
221	PERIPH_ID_EX_RESERVED47,
222
223	PERIPH_ID_COUNT,
224	PERIPH_ID_NONE = -1,
225	};
226
227	enum pll_out_id {
228	PLL_OUT1,
229	PLL_OUT2,
230	PLL_OUT3,
231	PLL_OUT4
232	};
233
234	/*
235	* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
236	* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
237	* confusion bewteen PERIPH_ID_... and PERIPHC_...
238	*
239	* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
240	* confusing.
241	*/
242	enum periphc_internal_id {
243	/* 0x00 */
244	PERIPHC_I2S1,
245	PERIPHC_I2S2,
246	PERIPHC_SPDIF_OUT,
247	PERIPHC_SPDIF_IN,
248	PERIPHC_PWM,
249	PERIPHC_05h,
250	PERIPHC_SBC2,
251	PERIPHC_SBC3,
252
253	/* 0x08 */
254	PERIPHC_08h,
255	PERIPHC_I2C1,
256	PERIPHC_DVC_I2C,
257	PERIPHC_0bh,
258	PERIPHC_0ch,
259	PERIPHC_SBC1,
260	PERIPHC_DISP1,
261	PERIPHC_DISP2,
262
263	/* 0x10 */
264	PERIPHC_CVE,
265	PERIPHC_11h,
266	PERIPHC_VI,
267	PERIPHC_13h,
268	PERIPHC_SDMMC1,
269	PERIPHC_SDMMC2,
270	PERIPHC_G3D,
271	PERIPHC_G2D,
272
273	/* 0x18 */
274	PERIPHC_NDFLASH,
275	PERIPHC_SDMMC4,
276	PERIPHC_VFIR,
277	PERIPHC_EPP,
278	PERIPHC_MPE,
279	PERIPHC_MIPI,
280	PERIPHC_UART1,
281	PERIPHC_UART2,
282
283	/* 0x20 */
284	PERIPHC_HOST1X,
285	PERIPHC_21h,
286	PERIPHC_TVO,
287	PERIPHC_HDMI,
288	PERIPHC_24h,
289	PERIPHC_TVDAC,
290	PERIPHC_I2C2,
291	PERIPHC_EMC,
292
293	/* 0x28 */
294	PERIPHC_UART3,
295	PERIPHC_29h,
296	PERIPHC_VI_SENSOR,
297	PERIPHC_2bh,
298	PERIPHC_2ch,
299	PERIPHC_SBC4,
300	PERIPHC_I2C3,
301	PERIPHC_SDMMC3,
302
303	/* 0x30 */
304	PERIPHC_UART4,
305	PERIPHC_UART5,
306	PERIPHC_VDE,
307	PERIPHC_OWR,
308	PERIPHC_NOR,
309	PERIPHC_CSITE,
310	PERIPHC_I2S0,
311	PERIPHC_37h,
312
313	PERIPHC_VW_FIRST,
314	/* 0x38 */
315	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
316	PERIPHC_MSELECT,
317	PERIPHC_TSENSOR,
318	PERIPHC_I2S3,
319	PERIPHC_I2S4,
320	PERIPHC_I2C4,
321	PERIPHC_SBC5,
322	PERIPHC_SBC6,
323
324	/* 0x40 */
325	PERIPHC_AUDIO,
326	PERIPHC_41h,
327	PERIPHC_DAM0,
328	PERIPHC_DAM1,
329	PERIPHC_DAM2,
330	PERIPHC_HDA2CODEC2X,
331	PERIPHC_ACTMON,
332	PERIPHC_EXTPERIPH1,
333
334	/* 0x48 */
335	PERIPHC_EXTPERIPH2,
336	PERIPHC_EXTPERIPH3,
337	PERIPHC_NANDSPEED,
338	PERIPHC_I2CSLOW,
339	PERIPHC_SYS,
340	PERIPHC_SPEEDO,
341	PERIPHC_4eh,
342	PERIPHC_4fh,
343
344	/* 0x50 */
619bd99e TW	345	PERIPHC_50h,
	346	PERIPHC_51h,
	347	PERIPHC_52h,
	348	PERIPHC_53h,
dc89ad14 TW	349	PERIPHC_SATAOOB,
	350	PERIPHC_SATA,
	351	PERIPHC_HDA,
	352
	353	PERIPHC_COUNT,
	354
	355	PERIPHC_NONE = -1,
	356	};
	357
	358	/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
	359	#define PERIPH_REG(id) \
	360	(id < PERIPH_ID_VW_FIRST) ? \
	361	((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
	362
	363	/* Mask value for a clock (within PERIPH_REG(id)) */
	364	#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
	365
	366	/* return 1 if a PLL ID is in range */
	367	#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
	368
	369	/* return 1 if a peripheral ID is in range */
	370	#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
	371	(id) < PERIPH_ID_COUNT)
	372
	373	#endif /* _TEGRA30_CLOCK_TABLES_H_ */