[people/ms/u-boot.git] / arch / arm / include / asm / arch-zynq / hardware.h

/*
 * Copyright (c) 2013 Xilinx Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H

#define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
#define ZYNQ_SCU_BASEADDR		0xF8F00000
#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
#define ZYNQ_GEM_BASEADDR0		0xE000B000
#define ZYNQ_GEM_BASEADDR1		0xE000C000
#define ZYNQ_SDHCI_BASEADDR0		0xE0100000
#define ZYNQ_SDHCI_BASEADDR1		0xE0101000
#define ZYNQ_I2C_BASEADDR0		0xE0004000
#define ZYNQ_I2C_BASEADDR1		0xE0005000

/* Reflect slcr offsets */
struct slcr_regs {
	u32 scl; /* 0x0 */
	u32 slcr_lock; /* 0x4 */
	u32 slcr_unlock; /* 0x8 */
	u32 reserved0[75];
	u32 gem0_rclk_ctrl; /* 0x138 */
	u32 gem1_rclk_ctrl; /* 0x13c */
	u32 gem0_clk_ctrl; /* 0x140 */
	u32 gem1_clk_ctrl; /* 0x144 */
	u32 reserved1[46];
	u32 pss_rst_ctrl; /* 0x200 */
	u32 reserved2[15];
	u32 fpga_rst_ctrl; /* 0x240 */
	u32 reserved3[5];
	u32 reboot_status; /* 0x258 */
	u32 boot_mode; /* 0x25c */
	u32 reserved4[116];
	u32 trust_zone; /* 0x430 */ /* FIXME */
	u32 reserved5_1[63];
	u32 pss_idcode; /* 0x530 */
	u32 reserved5_2[51];
	u32 ddr_urgent; /* 0x600 */
	u32 reserved6[6];
	u32 ddr_urgent_sel; /* 0x61c */
	u32 reserved7[56];
	u32 mio_pin[54]; /* 0x700 - 0x7D4 */
	u32 reserved8[74];
	u32 lvl_shftr_en; /* 0x900 */
	u32 reserved9[3];
	u32 ocm_cfg; /* 0x910 */
};

#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)

struct devcfg_regs {
	u32 ctrl; /* 0x0 */
	u32 lock; /* 0x4 */
	u32 cfg; /* 0x8 */
	u32 int_sts; /* 0xc */
	u32 int_mask; /* 0x10 */
	u32 status; /* 0x14 */
	u32 dma_src_addr; /* 0x18 */
	u32 dma_dst_addr; /* 0x1c */
	u32 dma_src_len; /* 0x20 */
	u32 dma_dst_len; /* 0x24 */
	u32 rom_shadow; /* 0x28 */
	u32 reserved1[2];
	u32 unlock; /* 0x34 */
	u32 reserved2[18];
	u32 mctrl; /* 0x80 */
	u32 reserved3;
	u32 write_count; /* 0x88 */
	u32 read_count; /* 0x8c */
};

#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)

struct scu_regs {
	u32 reserved1[16];
	u32 filter_start; /* 0x40 */
	u32 filter_end; /* 0x44 */
};

#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)

#endif /* _ASM_ARCH_HARDWARE_H */
Commit	Line	Data
59c651f4 MS	1	/*
	2	* Copyright (c) 2013 Xilinx Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
59c651f4 MS	5	*/
	6
	7	#ifndef _ASM_ARCH_HARDWARE_H
	8	#define _ASM_ARCH_HARDWARE_H
	9
e072b5f5 MS	10	#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
	11	#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
	12	#define ZYNQ_SCU_BASEADDR 0xF8F00000
4b21284b	13	#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
7193653e MS	14	#define ZYNQ_GEM_BASEADDR0 0xE000B000
7193653e MS	15	#define ZYNQ_GEM_BASEADDR1 0xE000C000
293eb33f MS	16	#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
293eb33f MS	17	#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
8934f784 MS	18	#define ZYNQ_I2C_BASEADDR0 0xE0004000
8934f784 MS	19	#define ZYNQ_I2C_BASEADDR1 0xE0005000
59c651f4 MS	20
	21	/* Reflect slcr offsets */
	22	struct slcr_regs {
	23	u32 scl; /* 0x0 */
	24	u32 slcr_lock; /* 0x4 */
	25	u32 slcr_unlock; /* 0x8 */
80243528 MS	26	u32 reserved0[75];
	27	u32 gem0_rclk_ctrl; /* 0x138 */
	28	u32 gem1_rclk_ctrl; /* 0x13c */
	29	u32 gem0_clk_ctrl; /* 0x140 */
	30	u32 gem1_clk_ctrl; /* 0x144 */
	31	u32 reserved1[46];
59c651f4	32	u32 pss_rst_ctrl; /* 0x200 */
00ed3458 MS	33	u32 reserved2[15];
	34	u32 fpga_rst_ctrl; /* 0x240 */
	35	u32 reserved3[5];
59c651f4	36	u32 reboot_status; /* 0x258 */
00ed3458 MS	37	u32 boot_mode; /* 0x25c */
	38	u32 reserved4[116];
	39	u32 trust_zone; /* 0x430 / / FIXME */
d5dae85f MS	40	u32 reserved5_1[63];
	41	u32 pss_idcode; /* 0x530 */
	42	u32 reserved5_2[51];
00ed3458 MS	43	u32 ddr_urgent; /* 0x600 */
	44	u32 reserved6[6];
	45	u32 ddr_urgent_sel; /* 0x61c */
d5dae85f MS	46	u32 reserved7[56];
	47	u32 mio_pin[54]; /* 0x700 - 0x7D4 */
	48	u32 reserved8[74];
	49	u32 lvl_shftr_en; /* 0x900 */
	50	u32 reserved9[3];
00ed3458	51	u32 ocm_cfg; /* 0x910 */
59c651f4 MS	52	};
59c651f4 MS	53
e072b5f5	54	#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
59c651f4	55
00ed3458 MS	56	struct devcfg_regs {
	57	u32 ctrl; /* 0x0 */
	58	u32 lock; /* 0x4 */
	59	u32 cfg; /* 0x8 */
	60	u32 int_sts; /* 0xc */
	61	u32 int_mask; /* 0x10 */
	62	u32 status; /* 0x14 */
	63	u32 dma_src_addr; /* 0x18 */
	64	u32 dma_dst_addr; /* 0x1c */
	65	u32 dma_src_len; /* 0x20 */
	66	u32 dma_dst_len; /* 0x24 */
	67	u32 rom_shadow; /* 0x28 */
	68	u32 reserved1[2];
	69	u32 unlock; /* 0x34 */
	70	u32 reserved2[18];
	71	u32 mctrl; /* 0x80 */
	72	u32 reserved3;
	73	u32 write_count; /* 0x88 */
	74	u32 read_count; /* 0x8c */
	75	};
	76
e072b5f5	77	#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
00ed3458 MS	78
	79	struct scu_regs {
	80	u32 reserved1[16];
	81	u32 filter_start; /* 0x40 */
	82	u32 filter_end; /* 0x44 */
	83	};
	84
e072b5f5	85	#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
00ed3458	86
59c651f4	87	#endif /* _ASM_ARCH_HARDWARE_H */