[people/ms/u-boot.git] / arch / arm / include / asm / armv7.h

/*
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 * Aneesh V <aneesh@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef ARMV7_H
#define ARMV7_H

/* Cortex-A9 revisions */
#define MIDR_CORTEX_A9_R0P1	0x410FC091
#define MIDR_CORTEX_A9_R1P2	0x411FC092
#define MIDR_CORTEX_A9_R1P3	0x411FC093
#define MIDR_CORTEX_A9_R2P10	0x412FC09A

/* Cortex-A15 revisions */
#define MIDR_CORTEX_A15_R0P0	0x410FC0F0
#define MIDR_CORTEX_A15_R2P2	0x412FC0F2

/* Cortex-A7 revisions */
#define MIDR_CORTEX_A7_R0P0	0x410FC070

#define MIDR_PRIMARY_PART_MASK	0xFF0FFFF0

/* ID_PFR1 feature fields */
#define CPUID_ARM_SEC_SHIFT		4
#define CPUID_ARM_SEC_MASK		(0xF << CPUID_ARM_SEC_SHIFT)
#define CPUID_ARM_VIRT_SHIFT		12
#define CPUID_ARM_VIRT_MASK		(0xF << CPUID_ARM_VIRT_SHIFT)
#define CPUID_ARM_GENTIMER_SHIFT	16
#define CPUID_ARM_GENTIMER_MASK		(0xF << CPUID_ARM_GENTIMER_SHIFT)

/* valid bits in CBAR register / PERIPHBASE value */
#define CBAR_MASK			0xFFFF8000

/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET		0
#define CCSIDR_LINE_SIZE_MASK		0x7
#define CCSIDR_ASSOCIATIVITY_OFFSET	3
#define CCSIDR_ASSOCIATIVITY_MASK	(0x3FF << 3)
#define CCSIDR_NUM_SETS_OFFSET		13
#define CCSIDR_NUM_SETS_MASK		(0x7FFF << 13)

/*
 * Values for InD field in CSSELR
 * Selects the type of cache
 */
#define ARMV7_CSSELR_IND_DATA_UNIFIED	0
#define ARMV7_CSSELR_IND_INSTRUCTION	1

/* Values for Ctype fields in CLIDR */
#define ARMV7_CLIDR_CTYPE_NO_CACHE		0
#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY	1
#define ARMV7_CLIDR_CTYPE_DATA_ONLY		2
#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA	3
#define ARMV7_CLIDR_CTYPE_UNIFIED		4

#ifndef __ASSEMBLY__
#include <linux/types.h>

/*
 * CP15 Barrier instructions
 * Please note that we have separate barrier instructions in ARMv7
 * However, we use the CP15 based instructtions because we use
 * -march=armv5 in U-Boot
 */
#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))

void v7_outer_cache_enable(void);
void v7_outer_cache_disable(void);
void v7_outer_cache_flush_all(void);
void v7_outer_cache_inval_all(void);
void v7_outer_cache_flush_range(u32 start, u32 end);
void v7_outer_cache_inval_range(u32 start, u32 end);

#ifdef CONFIG_ARMV7_NONSEC

int armv7_switch_nonsec(void);

/* defined in assembly file */
unsigned int _nonsec_init(void);
void _smp_pen(void);
#endif /* CONFIG_ARMV7_NONSEC */

#endif /* ! __ASSEMBLY__ */

#endif
Commit	Line	Data
2c451f78 A	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments, <www.ti.com>
	4	* Aneesh V <aneesh@ti.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
2c451f78 A	7	*/
	8	#ifndef ARMV7_H
	9	#define ARMV7_H
2c451f78	10
ad577c8a A	11	/* Cortex-A9 revisions */
	12	#define MIDR_CORTEX_A9_R0P1 0x410FC091
	13	#define MIDR_CORTEX_A9_R1P2 0x411FC092
	14	#define MIDR_CORTEX_A9_R1P3 0x411FC093
5ab12a9e	15	#define MIDR_CORTEX_A9_R2P10 0x412FC09A
ad577c8a	16
508a58fa S	17	/* Cortex-A15 revisions */
508a58fa S	18	#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
eed7c0f7	19	#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
508a58fa	20
16212b59 AP	21	/* Cortex-A7 revisions */
	22	#define MIDR_CORTEX_A7_R0P0 0x410FC070
	23
	24	#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
	25
	26	/* ID_PFR1 feature fields */
	27	#define CPUID_ARM_SEC_SHIFT 4
	28	#define CPUID_ARM_SEC_MASK (0xF << CPUID_ARM_SEC_SHIFT)
	29	#define CPUID_ARM_VIRT_SHIFT 12
	30	#define CPUID_ARM_VIRT_MASK (0xF << CPUID_ARM_VIRT_SHIFT)
	31	#define CPUID_ARM_GENTIMER_SHIFT 16
	32	#define CPUID_ARM_GENTIMER_MASK (0xF << CPUID_ARM_GENTIMER_SHIFT)
	33
	34	/* valid bits in CBAR register / PERIPHBASE value */
	35	#define CBAR_MASK 0xFFFF8000
	36
2c451f78 A	37	/* CCSIDR */
	38	#define CCSIDR_LINE_SIZE_OFFSET 0
	39	#define CCSIDR_LINE_SIZE_MASK 0x7
	40	#define CCSIDR_ASSOCIATIVITY_OFFSET 3
	41	#define CCSIDR_ASSOCIATIVITY_MASK (0x3FF << 3)
	42	#define CCSIDR_NUM_SETS_OFFSET 13
	43	#define CCSIDR_NUM_SETS_MASK (0x7FFF << 13)
	44
	45	/*
	46	* Values for InD field in CSSELR
	47	* Selects the type of cache
	48	*/
	49	#define ARMV7_CSSELR_IND_DATA_UNIFIED 0
	50	#define ARMV7_CSSELR_IND_INSTRUCTION 1
	51
	52	/* Values for Ctype fields in CLIDR */
	53	#define ARMV7_CLIDR_CTYPE_NO_CACHE 0
	54	#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY 1
	55	#define ARMV7_CLIDR_CTYPE_DATA_ONLY 2
	56	#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3
	57	#define ARMV7_CLIDR_CTYPE_UNIFIED 4
	58
d75ba503 AP	59	#ifndef __ASSEMBLY__
	60	#include <linux/types.h>
	61
2c451f78 A	62	/*
	63	* CP15 Barrier instructions
	64	* Please note that we have separate barrier instructions in ARMv7
	65	* However, we use the CP15 based instructtions because we use
	66	* -march=armv5 in U-Boot
	67	*/
	68	#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
	69	#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
	70	#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
	71
	72	void v7_outer_cache_enable(void);
	73	void v7_outer_cache_disable(void);
	74	void v7_outer_cache_flush_all(void);
	75	void v7_outer_cache_inval_all(void);
	76	void v7_outer_cache_flush_range(u32 start, u32 end);
	77	void v7_outer_cache_inval_range(u32 start, u32 end);
	78
16212b59	79	#ifdef CONFIG_ARMV7_NONSEC
1ef92385 AP	80
	81	int armv7_switch_nonsec(void);
	82
16212b59 AP	83	/* defined in assembly file */
16212b59 AP	84	unsigned int _nonsec_init(void);
ba6a1698	85	void _smp_pen(void);
16212b59 AP	86	#endif /* CONFIG_ARMV7_NONSEC */
16212b59 AP	87
d75ba503 AP	88	#endif /* ! __ASSEMBLY__ */
d75ba503 AP	89
2c451f78	90	#endif