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Commit | Line | Data |
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0157cedb | 1 | /* |
91a76751 | 2 | * (C) Copyright 2002-2010 |
0157cedb WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0157cedb WD |
6 | */ |
7 | ||
8 | #ifndef __ASM_GBL_DATA_H | |
9 | #define __ASM_GBL_DATA_H | |
5cb48582 SG |
10 | |
11 | /* Architecture-specific global data */ | |
12 | struct arch_global_data { | |
e9adeca3 SG |
13 | #if defined(CONFIG_FSL_ESDHC) |
14 | u32 sdhc_clk; | |
15 | #endif | |
93d33204 ZQ |
16 | |
17 | #if defined(CONFIG_U_QE) | |
18 | u32 qe_clk; | |
19 | u32 brg_clk; | |
20 | uint mp_alloc_base; | |
21 | uint mp_alloc_top; | |
22 | #endif /* CONFIG_U_QE */ | |
23 | ||
f47e6ecd SG |
24 | #ifdef CONFIG_AT91FAMILY |
25 | /* "static data" needed by at91's clock.c */ | |
26 | unsigned long cpu_clk_rate_hz; | |
27 | unsigned long main_clk_rate_hz; | |
28 | unsigned long mck_rate_hz; | |
29 | unsigned long plla_rate_hz; | |
30 | unsigned long pllb_rate_hz; | |
31 | unsigned long at91_pllb_usb_init; | |
32 | #endif | |
b339051c SG |
33 | /* "static data" needed by most of timer.c on ARM platforms */ |
34 | unsigned long timer_rate_hz; | |
8ff43b03 | 35 | unsigned long tbu; |
66ee6923 | 36 | unsigned long tbl; |
582601da | 37 | unsigned long lastinc; |
5f70714c | 38 | unsigned long long timer_reset_value; |
34fd5d25 SG |
39 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) |
40 | unsigned long tlb_addr; | |
5e2ec773 | 41 | unsigned long tlb_size; |
7985cdf7 | 42 | #if defined(CONFIG_ARM64) |
5e2ec773 AG |
43 | unsigned long tlb_fillptr; |
44 | unsigned long tlb_emerg; | |
94f7ff36 | 45 | #endif |
34fd5d25 | 46 | #endif |
e61a7534 YS |
47 | #ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
48 | #define MEM_RESERVE_SECURE_SECURED 0x1 | |
49 | #define MEM_RESERVE_SECURE_MAINTAINED 0x2 | |
50 | #define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) | |
51 | /* | |
52 | * Secure memory addr | |
53 | * This variable needs maintenance if the RAM base is not zero, | |
54 | * or if RAM splits into non-consecutive banks. It also has a | |
55 | * flag indicating the secure memory is marked as secure by MMU. | |
56 | * Flags used: 0x1 secured | |
57 | * 0x2 maintained | |
58 | */ | |
59 | phys_addr_t secure_ram; | |
50e93b95 | 60 | unsigned long tlb_allocated; |
e61a7534 | 61 | #endif |
f2ccf7f7 YS |
62 | #ifdef CONFIG_RESV_RAM |
63 | /* | |
64 | * Reserved RAM for memory resident, eg. Management Complex (MC) | |
65 | * driver which continues to run after U-Boot exits. | |
66 | */ | |
67 | phys_addr_t resv_ram; | |
68 | #endif | |
fda06812 | 69 | |
a93fbf4a | 70 | #ifdef CONFIG_ARCH_OMAP2PLUS |
60c7c30a PK |
71 | u32 omap_boot_device; |
72 | u32 omap_boot_mode; | |
73 | u8 omap_ch_flags; | |
fda06812 | 74 | #endif |
44937214 | 75 | #if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR) |
b87e6f88 YS |
76 | unsigned long mem2_clk; |
77 | #endif | |
5cb48582 SG |
78 | }; |
79 | ||
baa1e536 | 80 | #include <asm-generic/global_data.h> |
0157cedb | 81 | |
c65a2abb JH |
82 | #ifdef __clang__ |
83 | ||
84 | #define DECLARE_GLOBAL_DATA_PTR | |
85 | #define gd get_gd() | |
86 | ||
87 | static inline gd_t *get_gd(void) | |
88 | { | |
89 | gd_t *gd_ptr; | |
90 | ||
91 | #ifdef CONFIG_ARM64 | |
92 | /* | |
93 | * Make will already error that reserving x18 is not supported at the | |
94 | * time of writing, clang: error: unknown argument: '-ffixed-x18' | |
95 | */ | |
96 | __asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr)); | |
97 | #else | |
98 | __asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr)); | |
99 | #endif | |
100 | ||
101 | return gd_ptr; | |
102 | } | |
103 | ||
104 | #else | |
105 | ||
0ae76531 DF |
106 | #ifdef CONFIG_ARM64 |
107 | #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") | |
108 | #else | |
109 | #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9") | |
110 | #endif | |
c65a2abb | 111 | #endif |
0157cedb WD |
112 | |
113 | #endif /* __ASM_GBL_DATA_H */ |