[people/ms/u-boot.git] / arch / arm / include / asm / mach-imx / regs-common.h

/*
 * Freescale i.MXS Register Accessors
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MXS_REGS_COMMON_H__
#define __MXS_REGS_COMMON_H__

#include <linux/types.h>

/*
 * The i.MXS has interesting feature when it comes to register access. There
 * are four kinds of access to one particular register. Those are:
 *
 * 1) Common read/write access. To use this mode, just write to the address of
 *    the register.
 * 2) Set bits only access. To set bits, write which bits you want to set to the
 *    address of the register + 0x4.
 * 3) Clear bits only access. To clear bits, write which bits you want to clear
 *    to the address of the register + 0x8.
 * 4) Toggle bits only access. To toggle bits, write which bits you want to
 *    toggle to the address of the register + 0xc.
 *
 * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
 * can be set/cleared by pure write as in access type 1, some need to be
 * explicitly set/cleared by using access type 2-3.
 *
 * The following macros and structures allow the user to either access the
 * register in all aforementioned modes (by accessing reg_name, reg_name_set,
 * reg_name_clr, reg_name_tog) or pass the register structure further into
 * various functions with correct type information (by accessing reg_name_reg).
 *
 */

#define	__mxs_reg_8(name)		\
	uint8_t	name[4];		\
	uint8_t	name##_set[4];		\
	uint8_t	name##_clr[4];		\
	uint8_t	name##_tog[4];		\

#define	__mxs_reg_32(name)		\
	uint32_t name;			\
	uint32_t name##_set;		\
	uint32_t name##_clr;		\
	uint32_t name##_tog;

struct mxs_register_8 {
	__mxs_reg_8(reg)
};

struct mxs_register_32 {
	__mxs_reg_32(reg)
};

#define	mxs_reg_8(name)				\
	union {						\
		struct { __mxs_reg_8(name) };		\
		struct mxs_register_8 name##_reg;	\
	};

#define	mxs_reg_32(name)				\
	union {						\
		struct { __mxs_reg_32(name) };		\
		struct mxs_register_32 name##_reg;	\
	};

#endif	/* __MXS_REGS_COMMON_H__ */
Commit	Line	Data
6e9a0a39	1	/*
ddcf13b1	2	* Freescale i.MXS Register Accessors
6e9a0a39 MV	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
6e9a0a39 MV	8	*/
6e9a0a39 MV	9
ddcf13b1 OS	10	#ifndef __MXS_REGS_COMMON_H__
ddcf13b1 OS	11	#define __MXS_REGS_COMMON_H__
6e9a0a39	12
eacb2875 PF	13	#include <linux/types.h>
eacb2875 PF	14
6e9a0a39	15	/*
ddcf13b1	16	* The i.MXS has interesting feature when it comes to register access. There
6e9a0a39 MV	17	* are four kinds of access to one particular register. Those are:
	18	*
	19	* 1) Common read/write access. To use this mode, just write to the address of
	20	* the register.
	21	* 2) Set bits only access. To set bits, write which bits you want to set to the
	22	* address of the register + 0x4.
	23	* 3) Clear bits only access. To clear bits, write which bits you want to clear
	24	* to the address of the register + 0x8.
	25	* 4) Toggle bits only access. To toggle bits, write which bits you want to
	26	* toggle to the address of the register + 0xc.
	27	*
	28	* IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
	29	* can be set/cleared by pure write as in access type 1, some need to be
	30	* explicitly set/cleared by using access type 2-3.
	31	*
	32	* The following macros and structures allow the user to either access the
	33	* register in all aforementioned modes (by accessing reg_name, reg_name_set,
	34	* reg_name_clr, reg_name_tog) or pass the register structure further into
	35	* various functions with correct type information (by accessing reg_name_reg).
	36	*
	37	*/
	38
ddcf13b1	39	#define __mxs_reg_8(name) \
531bb825 RD	40	uint8_t name[4]; \
	41	uint8_t name##_set[4]; \
	42	uint8_t name##_clr[4]; \
	43	uint8_t name##_tog[4]; \
	44
ddcf13b1	45	#define __mxs_reg_32(name) \
6e9a0a39 MV	46	uint32_t name; \
	47	uint32_t name##_set; \
	48	uint32_t name##_clr; \
	49	uint32_t name##_tog;
	50
ddcf13b1 OS	51	struct mxs_register_8 {
ddcf13b1 OS	52	__mxs_reg_8(reg)
531bb825 RD	53	};
531bb825 RD	54
ddcf13b1 OS	55	struct mxs_register_32 {
ddcf13b1 OS	56	__mxs_reg_32(reg)
6e9a0a39 MV	57	};
6e9a0a39 MV	58
ddcf13b1	59	#define mxs_reg_8(name) \
531bb825	60	union { \
ddcf13b1 OS	61	struct { __mxs_reg_8(name) }; \
ddcf13b1 OS	62	struct mxs_register_8 name##_reg; \
531bb825 RD	63	};
531bb825 RD	64
ddcf13b1	65	#define mxs_reg_32(name) \
6e9a0a39	66	union { \
ddcf13b1 OS	67	struct { __mxs_reg_32(name) }; \
ddcf13b1 OS	68	struct mxs_register_32 name##_reg; \
6e9a0a39 MV	69	};
6e9a0a39 MV	70
ddcf13b1	71	#endif /* __MXS_REGS_COMMON_H__ */