projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6e9a0a39 MV |
1 | /* |
| 2 | * Freescale i.MX28 GPMI Register Definitions | |
| 3 | * | |
| 4 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
| 5 | * on behalf of DENX Software Engineering GmbH | |
| 6 | * | |
| 7 | * Based on code from LTIB: | |
| 8 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 9 | * | |
| 1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
| 6e9a0a39 MV |
11 | */ |
| 12 | ||
| 13 | #ifndef __MX28_REGS_GPMI_H__ | |
| 14 | #define __MX28_REGS_GPMI_H__ | |
| 15 | ||
| 552a848e | 16 | #include <asm/mach-imx/regs-common.h> |
| 6e9a0a39 MV |
17 | |
| 18 | #ifndef __ASSEMBLY__ | |
| 9c471142 | 19 | struct mxs_gpmi_regs { |
| ddcf13b1 OS |
20 | mxs_reg_32(hw_gpmi_ctrl0) |
| 21 | mxs_reg_32(hw_gpmi_compare) | |
| 22 | mxs_reg_32(hw_gpmi_eccctrl) | |
| 23 | mxs_reg_32(hw_gpmi_ecccount) | |
| 24 | mxs_reg_32(hw_gpmi_payload) | |
| 25 | mxs_reg_32(hw_gpmi_auxiliary) | |
| 26 | mxs_reg_32(hw_gpmi_ctrl1) | |
| 27 | mxs_reg_32(hw_gpmi_timing0) | |
| 28 | mxs_reg_32(hw_gpmi_timing1) | |
| 6e9a0a39 MV |
29 | |
| 30 | uint32_t reserved[4]; | |
| 31 | ||
| ddcf13b1 OS |
32 | mxs_reg_32(hw_gpmi_data) |
| 33 | mxs_reg_32(hw_gpmi_stat) | |
| 34 | mxs_reg_32(hw_gpmi_debug) | |
| 35 | mxs_reg_32(hw_gpmi_version) | |
| 6e9a0a39 MV |
36 | }; |
| 37 | #endif | |
| 38 | ||
| 39 | #define GPMI_CTRL0_SFTRST (1 << 31) | |
| 40 | #define GPMI_CTRL0_CLKGATE (1 << 30) | |
| 41 | #define GPMI_CTRL0_RUN (1 << 29) | |
| 42 | #define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) | |
| 43 | #define GPMI_CTRL0_LOCK_CS (1 << 27) | |
| 44 | #define GPMI_CTRL0_UDMA (1 << 26) | |
| 45 | #define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) | |
| 46 | #define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 | |
| 47 | #define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) | |
| 48 | #define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) | |
| 49 | #define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) | |
| 50 | #define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) | |
| 51 | #define GPMI_CTRL0_WORD_LENGTH (1 << 23) | |
| 52 | #define GPMI_CTRL0_CS_MASK (0x7 << 20) | |
| 53 | #define GPMI_CTRL0_CS_OFFSET 20 | |
| 54 | #define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) | |
| 55 | #define GPMI_CTRL0_ADDRESS_OFFSET 17 | |
| 56 | #define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) | |
| 57 | #define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) | |
| 58 | #define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) | |
| 59 | #define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) | |
| 60 | #define GPMI_CTRL0_XFER_COUNT_MASK 0xffff | |
| 61 | #define GPMI_CTRL0_XFER_COUNT_OFFSET 0 | |
| 62 | ||
| 63 | #define GPMI_COMPARE_MASK_MASK (0xffff << 16) | |
| 64 | #define GPMI_COMPARE_MASK_OFFSET 16 | |
| 65 | #define GPMI_COMPARE_REFERENCE_MASK 0xffff | |
| 66 | #define GPMI_COMPARE_REFERENCE_OFFSET 0 | |
| 67 | ||
| 68 | #define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) | |
| 69 | #define GPMI_ECCCTRL_HANDLE_OFFSET 16 | |
| 70 | #define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) | |
| 71 | #define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 | |
| 72 | #define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) | |
| 73 | #define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) | |
| 74 | #define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) | |
| 75 | #define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff | |
| 76 | #define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 | |
| 77 | #define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 | |
| 78 | #define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff | |
| 79 | ||
| 80 | #define GPMI_ECCCOUNT_COUNT_MASK 0xffff | |
| 81 | #define GPMI_ECCCOUNT_COUNT_OFFSET 0 | |
| 82 | ||
| 83 | #define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) | |
| 84 | #define GPMI_PAYLOAD_ADDRESS_OFFSET 2 | |
| 85 | ||
| 86 | #define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) | |
| 87 | #define GPMI_AUXILIARY_ADDRESS_OFFSET 2 | |
| 88 | ||
| 89 | #define GPMI_CTRL1_DECOUPLE_CS (1 << 24) | |
| 90 | #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) | |
| 91 | #define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 | |
| 92 | #define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) | |
| 93 | #define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) | |
| 94 | #define GPMI_CTRL1_BCH_MODE (1 << 18) | |
| 95 | #define GPMI_CTRL1_DLL_ENABLE (1 << 17) | |
| 96 | #define GPMI_CTRL1_HALF_PERIOD (1 << 16) | |
| 97 | #define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) | |
| 98 | #define GPMI_CTRL1_RDN_DELAY_OFFSET 12 | |
| 99 | #define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) | |
| 100 | #define GPMI_CTRL1_DEV_IRQ (1 << 10) | |
| 101 | #define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) | |
| 102 | #define GPMI_CTRL1_BURST_EN (1 << 8) | |
| 103 | #define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) | |
| 104 | #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) | |
| 105 | #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 | |
| 106 | #define GPMI_CTRL1_DEV_RESET (1 << 3) | |
| 107 | #define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) | |
| 108 | #define GPMI_CTRL1_CAMERA_MODE (1 << 1) | |
| 109 | #define GPMI_CTRL1_GPMI_MODE (1 << 0) | |
| 110 | ||
| 111 | #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) | |
| 112 | #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 | |
| 113 | #define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) | |
| 114 | #define GPMI_TIMING0_DATA_HOLD_OFFSET 8 | |
| 115 | #define GPMI_TIMING0_DATA_SETUP_MASK 0xff | |
| 116 | #define GPMI_TIMING0_DATA_SETUP_OFFSET 0 | |
| 117 | ||
| 118 | #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) | |
| 119 | #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 | |
| 120 | ||
| 121 | #define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) | |
| 122 | #define GPMI_TIMING2_UDMA_TRP_OFFSET 24 | |
| 123 | #define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) | |
| 124 | #define GPMI_TIMING2_UDMA_ENV_OFFSET 16 | |
| 125 | #define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) | |
| 126 | #define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 | |
| 127 | #define GPMI_TIMING2_UDMA_SETUP_MASK 0xff | |
| 128 | #define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 | |
| 129 | ||
| 130 | #define GPMI_DATA_DATA_MASK 0xffffffff | |
| 131 | #define GPMI_DATA_DATA_OFFSET 0 | |
| 132 | ||
| 133 | #define GPMI_STAT_READY_BUSY_MASK (0xff << 24) | |
| 134 | #define GPMI_STAT_READY_BUSY_OFFSET 24 | |
| 135 | #define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) | |
| 136 | #define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 | |
| 137 | #define GPMI_STAT_DEV7_ERROR (1 << 15) | |
| 138 | #define GPMI_STAT_DEV6_ERROR (1 << 14) | |
| 139 | #define GPMI_STAT_DEV5_ERROR (1 << 13) | |
| 140 | #define GPMI_STAT_DEV4_ERROR (1 << 12) | |
| 141 | #define GPMI_STAT_DEV3_ERROR (1 << 11) | |
| 142 | #define GPMI_STAT_DEV2_ERROR (1 << 10) | |
| 143 | #define GPMI_STAT_DEV1_ERROR (1 << 9) | |
| 144 | #define GPMI_STAT_DEV0_ERROR (1 << 8) | |
| 145 | #define GPMI_STAT_ATA_IRQ (1 << 4) | |
| 146 | #define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) | |
| 147 | #define GPMI_STAT_FIFO_EMPTY (1 << 2) | |
| 148 | #define GPMI_STAT_FIFO_FULL (1 << 1) | |
| 149 | #define GPMI_STAT_PRESENT (1 << 0) | |
| 150 | ||
| 151 | #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) | |
| 152 | #define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 | |
| 153 | #define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) | |
| 154 | #define GPMI_DEBUG_DMA_SENSE_OFFSET 16 | |
| 155 | #define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) | |
| 156 | #define GPMI_DEBUG_DMAREQ_OFFSET 8 | |
| 157 | #define GPMI_DEBUG_CMD_END_MASK 0xff | |
| 158 | #define GPMI_DEBUG_CMD_END_OFFSET 0 | |
| 159 | ||
| 160 | #define GPMI_VERSION_MAJOR_MASK (0xff << 24) | |
| 161 | #define GPMI_VERSION_MAJOR_OFFSET 24 | |
| 162 | #define GPMI_VERSION_MINOR_MASK (0xff << 16) | |
| 163 | #define GPMI_VERSION_MINOR_OFFSET 16 | |
| 164 | #define GPMI_VERSION_STEP_MASK 0xffff | |
| 165 | #define GPMI_VERSION_STEP_OFFSET 0 | |
| 166 | ||
| 167 | #define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) | |
| 168 | #define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 | |
| 169 | #define GPMI_DEBUG2_BUSY (1 << 23) | |
| 170 | #define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) | |
| 171 | #define GPMI_DEBUG2_PIN_STATE_OFFSET 20 | |
| 172 | #define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) | |
| 173 | #define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) | |
| 174 | #define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) | |
| 175 | #define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) | |
| 176 | #define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) | |
| 177 | #define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) | |
| 178 | #define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) | |
| 179 | #define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) | |
| 180 | #define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) | |
| 181 | #define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 | |
| 182 | #define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) | |
| 183 | #define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) | |
| 184 | #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) | |
| 185 | #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) | |
| 186 | #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) | |
| 187 | #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) | |
| 188 | #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) | |
| 189 | #define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) | |
| 190 | #define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) | |
| 191 | #define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) | |
| 192 | #define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) | |
| 193 | #define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) | |
| 194 | #define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 | |
| 195 | #define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) | |
| 196 | #define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) | |
| 197 | #define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) | |
| 198 | #define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) | |
| 199 | #define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) | |
| 200 | #define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) | |
| 201 | #define GPMI_DEBUG2_RDN_TAP_MASK 0x3f | |
| 202 | #define GPMI_DEBUG2_RDN_TAP_OFFSET 0 | |
| 203 | ||
| 204 | #define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) | |
| 205 | #define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 | |
| 206 | #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff | |
| 207 | #define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 | |
| 208 | ||
| 209 | #endif /* __MX28_REGS_GPMI_H__ */ |