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fc684e87 PF |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef _SYS_PROTO_H_ | |
9 | #define _SYS_PROTO_H_ | |
10 | ||
cba586b4 | 11 | #include <asm/io.h> |
552a848e | 12 | #include <asm/mach-imx/regs-common.h> |
fc684e87 PF |
13 | #include <common.h> |
14 | #include "../arch-imx/cpu.h" | |
15 | ||
16 | #define soc_rev() (get_cpu_rev() & 0xFF) | |
17 | #define is_soc_rev(rev) (soc_rev() == rev) | |
18 | ||
19 | /* returns MXC_CPU_ value */ | |
20 | #define cpu_type(rev) (((rev) >> 12) & 0xff) | |
15c52b3d | 21 | #define soc_type(rev) (((rev) >> 12) & 0xf0) |
fc684e87 PF |
22 | /* both macros return/take MXC_CPU_ constants */ |
23 | #define get_cpu_type() (cpu_type(get_cpu_rev())) | |
15c52b3d | 24 | #define get_soc_type() (soc_type(get_cpu_rev())) |
fc684e87 | 25 | #define is_cpu_type(cpu) (get_cpu_type() == cpu) |
15c52b3d | 26 | #define is_soc_type(soc) (get_soc_type() == soc) |
fc684e87 | 27 | |
32ff58bb PF |
28 | #define is_mx6() (is_soc_type(MXC_SOC_MX6)) |
29 | #define is_mx7() (is_soc_type(MXC_SOC_MX7)) | |
4fdffb98 | 30 | #define is_mx8m() (is_soc_type(MXC_SOC_MX8M)) |
32ff58bb | 31 | |
fc684e87 | 32 | #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) |
32ff58bb PF |
33 | #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) |
34 | #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) | |
f4b7532f | 35 | #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) |
32ff58bb PF |
36 | #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) |
37 | #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) | |
f4b7532f | 38 | #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) |
32ff58bb | 39 | #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) |
bbd1b07d | 40 | #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) |
7ce6d3c8 | 41 | #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) |
fc684e87 | 42 | |
3ca0f0d2 PF |
43 | #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) |
44 | ||
cba586b4 JT |
45 | #ifdef CONFIG_MX6 |
46 | #define IMX6_SRC_GPR10_BMODE BIT(28) | |
47 | ||
96aac843 JT |
48 | #define IMX6_BMODE_MASK GENMASK(7, 0) |
49 | #define IMX6_BMODE_SHIFT 4 | |
50 | #define IMX6_BMODE_EMI_MASK BIT(3) | |
51 | #define IMX6_BMODE_EMI_SHIFT 3 | |
52 | #define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24) | |
53 | #define IMX6_BMODE_SERIAL_ROM_SHIFT 24 | |
54 | ||
55 | enum imx6_bmode_serial_rom { | |
56 | IMX6_BMODE_ECSPI1, | |
57 | IMX6_BMODE_ECSPI2, | |
58 | IMX6_BMODE_ECSPI3, | |
59 | IMX6_BMODE_ECSPI4, | |
60 | IMX6_BMODE_ECSPI5, | |
61 | IMX6_BMODE_I2C1, | |
62 | IMX6_BMODE_I2C2, | |
63 | IMX6_BMODE_I2C3, | |
64 | }; | |
65 | ||
66 | enum imx6_bmode_emi { | |
67 | IMX6_BMODE_ONENAND, | |
68 | IMX6_BMODE_NOR, | |
69 | }; | |
70 | ||
71 | enum imx6_bmode { | |
72 | IMX6_BMODE_EMI, | |
3bd1642d SA |
73 | #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) |
74 | IMX6_BMODE_QSPI, | |
75 | IMX6_BMODE_RESERVED, | |
76 | #else | |
77 | IMX6_BMODE_RESERVED, | |
96aac843 | 78 | IMX6_BMODE_SATA, |
3bd1642d | 79 | #endif |
96aac843 JT |
80 | IMX6_BMODE_SERIAL_ROM, |
81 | IMX6_BMODE_SD, | |
82 | IMX6_BMODE_ESD, | |
83 | IMX6_BMODE_MMC, | |
84 | IMX6_BMODE_EMMC, | |
af104ae5 EM |
85 | IMX6_BMODE_NAND_MIN, |
86 | IMX6_BMODE_NAND_MAX = 0xf, | |
96aac843 JT |
87 | }; |
88 | ||
cba586b4 JT |
89 | static inline u8 imx6_is_bmode_from_gpr9(void) |
90 | { | |
7b54f5a8 | 91 | return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE; |
cba586b4 JT |
92 | } |
93 | ||
94 | u32 imx6_src_get_boot_mode(void); | |
3aa4b703 BL |
95 | void gpr_init(void); |
96 | ||
cba586b4 JT |
97 | #endif /* CONFIG_MX6 */ |
98 | ||
fc684e87 PF |
99 | u32 get_nr_cpus(void); |
100 | u32 get_cpu_rev(void); | |
101 | u32 get_cpu_speed_grade_hz(void); | |
102 | u32 get_cpu_temp_grade(int *minc, int *maxc); | |
103 | const char *get_imx_type(u32 imxtype); | |
104 | u32 imx_ddr_size(void); | |
105 | void sdelay(unsigned long); | |
106 | void set_chipselect_size(int const); | |
107 | ||
50a082a8 AA |
108 | void init_aips(void); |
109 | void init_src(void); | |
e2162d70 | 110 | void imx_wdog_disable_powerdown(void); |
50a082a8 | 111 | |
9f272573 DD |
112 | int board_mmc_get_env_dev(int devno); |
113 | ||
4555c261 FE |
114 | int nxp_board_rev(void); |
115 | char nxp_board_rev_string(void); | |
116 | ||
fc684e87 PF |
117 | /* |
118 | * Initializes on-chip ethernet controllers. | |
119 | * to override, implement board_eth_init() | |
120 | */ | |
121 | int fecmxc_initialize(bd_t *bis); | |
122 | u32 get_ahb_clk(void); | |
123 | u32 get_periph_clk(void); | |
124 | ||
a3c252d6 PF |
125 | void lcdif_power_down(void); |
126 | ||
fc684e87 PF |
127 | int mxs_reset_block(struct mxs_register_32 *reg); |
128 | int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); | |
129 | int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); | |
de274663 PF |
130 | |
131 | unsigned long call_imx_sip(unsigned long id, unsigned long reg0, | |
132 | unsigned long reg1, unsigned long reg2); | |
fc684e87 | 133 | #endif |