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Commit | Line | Data |
---|---|---|
d2f18c27 A |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Aneesh V <aneesh@ti.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
d2f18c27 A |
8 | */ |
9 | #ifndef _OMAP_COMMON_H_ | |
10 | #define _OMAP_COMMON_H_ | |
11 | ||
4a0eb757 S |
12 | #ifndef __ASSEMBLY__ |
13 | ||
01b753ff S |
14 | #include <common.h> |
15 | ||
97405d84 | 16 | #define NUM_SYS_CLKS 7 |
ee9447bf | 17 | |
01b753ff S |
18 | struct prcm_regs { |
19 | /* cm1.ckgen */ | |
20 | u32 cm_clksel_core; | |
21 | u32 cm_clksel_abe; | |
22 | u32 cm_dll_ctrl; | |
23 | u32 cm_clkmode_dpll_core; | |
24 | u32 cm_idlest_dpll_core; | |
25 | u32 cm_autoidle_dpll_core; | |
26 | u32 cm_clksel_dpll_core; | |
27 | u32 cm_div_m2_dpll_core; | |
28 | u32 cm_div_m3_dpll_core; | |
29 | u32 cm_div_h11_dpll_core; | |
30 | u32 cm_div_h12_dpll_core; | |
31 | u32 cm_div_h13_dpll_core; | |
32 | u32 cm_div_h14_dpll_core; | |
afc2f9dc S |
33 | u32 cm_div_h21_dpll_core; |
34 | u32 cm_div_h24_dpll_core; | |
01b753ff S |
35 | u32 cm_ssc_deltamstep_dpll_core; |
36 | u32 cm_ssc_modfreqdiv_dpll_core; | |
37 | u32 cm_emu_override_dpll_core; | |
38 | u32 cm_div_h22_dpllcore; | |
39 | u32 cm_div_h23_dpll_core; | |
40 | u32 cm_clkmode_dpll_mpu; | |
41 | u32 cm_idlest_dpll_mpu; | |
42 | u32 cm_autoidle_dpll_mpu; | |
43 | u32 cm_clksel_dpll_mpu; | |
44 | u32 cm_div_m2_dpll_mpu; | |
45 | u32 cm_ssc_deltamstep_dpll_mpu; | |
46 | u32 cm_ssc_modfreqdiv_dpll_mpu; | |
47 | u32 cm_bypclk_dpll_mpu; | |
48 | u32 cm_clkmode_dpll_iva; | |
49 | u32 cm_idlest_dpll_iva; | |
50 | u32 cm_autoidle_dpll_iva; | |
51 | u32 cm_clksel_dpll_iva; | |
52 | u32 cm_div_h11_dpll_iva; | |
53 | u32 cm_div_h12_dpll_iva; | |
54 | u32 cm_ssc_deltamstep_dpll_iva; | |
55 | u32 cm_ssc_modfreqdiv_dpll_iva; | |
56 | u32 cm_bypclk_dpll_iva; | |
57 | u32 cm_clkmode_dpll_abe; | |
58 | u32 cm_idlest_dpll_abe; | |
59 | u32 cm_autoidle_dpll_abe; | |
60 | u32 cm_clksel_dpll_abe; | |
61 | u32 cm_div_m2_dpll_abe; | |
62 | u32 cm_div_m3_dpll_abe; | |
63 | u32 cm_ssc_deltamstep_dpll_abe; | |
64 | u32 cm_ssc_modfreqdiv_dpll_abe; | |
65 | u32 cm_clkmode_dpll_ddrphy; | |
66 | u32 cm_idlest_dpll_ddrphy; | |
67 | u32 cm_autoidle_dpll_ddrphy; | |
68 | u32 cm_clksel_dpll_ddrphy; | |
69 | u32 cm_div_m2_dpll_ddrphy; | |
70 | u32 cm_div_h11_dpll_ddrphy; | |
71 | u32 cm_div_h12_dpll_ddrphy; | |
72 | u32 cm_div_h13_dpll_ddrphy; | |
73 | u32 cm_ssc_deltamstep_dpll_ddrphy; | |
d4e4129c | 74 | u32 cm_clkmode_dpll_dsp; |
01b753ff | 75 | u32 cm_shadow_freq_config1; |
65e9d56f | 76 | u32 cm_clkmode_dpll_gmac; |
01b753ff S |
77 | u32 cm_mpu_mpu_clkctrl; |
78 | ||
79 | /* cm1.dsp */ | |
80 | u32 cm_dsp_clkstctrl; | |
81 | u32 cm_dsp_dsp_clkctrl; | |
82 | ||
83 | /* cm1.abe */ | |
84 | u32 cm1_abe_clkstctrl; | |
85 | u32 cm1_abe_l4abe_clkctrl; | |
86 | u32 cm1_abe_aess_clkctrl; | |
87 | u32 cm1_abe_pdm_clkctrl; | |
88 | u32 cm1_abe_dmic_clkctrl; | |
89 | u32 cm1_abe_mcasp_clkctrl; | |
90 | u32 cm1_abe_mcbsp1_clkctrl; | |
91 | u32 cm1_abe_mcbsp2_clkctrl; | |
92 | u32 cm1_abe_mcbsp3_clkctrl; | |
93 | u32 cm1_abe_slimbus_clkctrl; | |
94 | u32 cm1_abe_timer5_clkctrl; | |
95 | u32 cm1_abe_timer6_clkctrl; | |
96 | u32 cm1_abe_timer7_clkctrl; | |
97 | u32 cm1_abe_timer8_clkctrl; | |
98 | u32 cm1_abe_wdt3_clkctrl; | |
99 | ||
100 | /* cm2.ckgen */ | |
101 | u32 cm_clksel_mpu_m3_iss_root; | |
102 | u32 cm_clksel_usb_60mhz; | |
103 | u32 cm_scale_fclk; | |
104 | u32 cm_core_dvfs_perf1; | |
105 | u32 cm_core_dvfs_perf2; | |
106 | u32 cm_core_dvfs_perf3; | |
107 | u32 cm_core_dvfs_perf4; | |
108 | u32 cm_core_dvfs_current; | |
109 | u32 cm_iva_dvfs_perf_tesla; | |
110 | u32 cm_iva_dvfs_perf_ivahd; | |
111 | u32 cm_iva_dvfs_perf_abe; | |
112 | u32 cm_iva_dvfs_current; | |
113 | u32 cm_clkmode_dpll_per; | |
114 | u32 cm_idlest_dpll_per; | |
115 | u32 cm_autoidle_dpll_per; | |
116 | u32 cm_clksel_dpll_per; | |
117 | u32 cm_div_m2_dpll_per; | |
118 | u32 cm_div_m3_dpll_per; | |
119 | u32 cm_div_h11_dpll_per; | |
120 | u32 cm_div_h12_dpll_per; | |
afc2f9dc | 121 | u32 cm_div_h13_dpll_per; |
01b753ff S |
122 | u32 cm_div_h14_dpll_per; |
123 | u32 cm_ssc_deltamstep_dpll_per; | |
124 | u32 cm_ssc_modfreqdiv_dpll_per; | |
125 | u32 cm_emu_override_dpll_per; | |
126 | u32 cm_clkmode_dpll_usb; | |
127 | u32 cm_idlest_dpll_usb; | |
128 | u32 cm_autoidle_dpll_usb; | |
129 | u32 cm_clksel_dpll_usb; | |
130 | u32 cm_div_m2_dpll_usb; | |
131 | u32 cm_ssc_deltamstep_dpll_usb; | |
132 | u32 cm_ssc_modfreqdiv_dpll_usb; | |
133 | u32 cm_clkdcoldo_dpll_usb; | |
d4e4129c LV |
134 | u32 cm_clkmode_dpll_pcie_ref; |
135 | u32 cm_clkmode_apll_pcie; | |
136 | u32 cm_idlest_apll_pcie; | |
137 | u32 cm_div_m2_apll_pcie; | |
138 | u32 cm_clkvcoldo_apll_pcie; | |
01b753ff S |
139 | u32 cm_clkmode_dpll_unipro; |
140 | u32 cm_idlest_dpll_unipro; | |
141 | u32 cm_autoidle_dpll_unipro; | |
142 | u32 cm_clksel_dpll_unipro; | |
143 | u32 cm_div_m2_dpll_unipro; | |
144 | u32 cm_ssc_deltamstep_dpll_unipro; | |
145 | u32 cm_ssc_modfreqdiv_dpll_unipro; | |
d3cfcb3e | 146 | u32 cm_coreaon_usb_phy1_core_clkctrl; |
834e91af | 147 | u32 cm_coreaon_usb_phy2_core_clkctrl; |
7beaf8b6 | 148 | u32 cm_coreaon_l3init_60m_gfclk_clkctrl; |
01b753ff S |
149 | |
150 | /* cm2.core */ | |
151 | u32 cm_coreaon_bandgap_clkctrl; | |
d4d986ee | 152 | u32 cm_coreaon_io_srcomp_clkctrl; |
01b753ff S |
153 | u32 cm_l3_1_clkstctrl; |
154 | u32 cm_l3_1_dynamicdep; | |
155 | u32 cm_l3_1_l3_1_clkctrl; | |
156 | u32 cm_l3_2_clkstctrl; | |
157 | u32 cm_l3_2_dynamicdep; | |
158 | u32 cm_l3_2_l3_2_clkctrl; | |
d4e4129c | 159 | u32 cm_l3_gpmc_clkctrl; |
01b753ff S |
160 | u32 cm_l3_2_ocmc_ram_clkctrl; |
161 | u32 cm_mpu_m3_clkstctrl; | |
162 | u32 cm_mpu_m3_staticdep; | |
163 | u32 cm_mpu_m3_dynamicdep; | |
164 | u32 cm_mpu_m3_mpu_m3_clkctrl; | |
165 | u32 cm_sdma_clkstctrl; | |
166 | u32 cm_sdma_staticdep; | |
167 | u32 cm_sdma_dynamicdep; | |
168 | u32 cm_sdma_sdma_clkctrl; | |
169 | u32 cm_memif_clkstctrl; | |
170 | u32 cm_memif_dmm_clkctrl; | |
171 | u32 cm_memif_emif_fw_clkctrl; | |
172 | u32 cm_memif_emif_1_clkctrl; | |
173 | u32 cm_memif_emif_2_clkctrl; | |
174 | u32 cm_memif_dll_clkctrl; | |
175 | u32 cm_memif_emif_h1_clkctrl; | |
176 | u32 cm_memif_emif_h2_clkctrl; | |
177 | u32 cm_memif_dll_h_clkctrl; | |
178 | u32 cm_c2c_clkstctrl; | |
179 | u32 cm_c2c_staticdep; | |
180 | u32 cm_c2c_dynamicdep; | |
181 | u32 cm_c2c_sad2d_clkctrl; | |
182 | u32 cm_c2c_modem_icr_clkctrl; | |
183 | u32 cm_c2c_sad2d_fw_clkctrl; | |
184 | u32 cm_l4cfg_clkstctrl; | |
185 | u32 cm_l4cfg_dynamicdep; | |
186 | u32 cm_l4cfg_l4_cfg_clkctrl; | |
187 | u32 cm_l4cfg_hw_sem_clkctrl; | |
188 | u32 cm_l4cfg_mailbox_clkctrl; | |
189 | u32 cm_l4cfg_sar_rom_clkctrl; | |
190 | u32 cm_l3instr_clkstctrl; | |
191 | u32 cm_l3instr_l3_3_clkctrl; | |
192 | u32 cm_l3instr_l3_instr_clkctrl; | |
193 | u32 cm_l3instr_intrconn_wp1_clkctrl; | |
194 | ||
195 | /* cm2.ivahd */ | |
196 | u32 cm_ivahd_clkstctrl; | |
197 | u32 cm_ivahd_ivahd_clkctrl; | |
198 | u32 cm_ivahd_sl2_clkctrl; | |
199 | ||
200 | /* cm2.cam */ | |
201 | u32 cm_cam_clkstctrl; | |
202 | u32 cm_cam_iss_clkctrl; | |
203 | u32 cm_cam_fdif_clkctrl; | |
d4e4129c LV |
204 | u32 cm_cam_vip1_clkctrl; |
205 | u32 cm_cam_vip2_clkctrl; | |
206 | u32 cm_cam_vip3_clkctrl; | |
207 | u32 cm_cam_lvdsrx_clkctrl; | |
208 | u32 cm_cam_csi1_clkctrl; | |
209 | u32 cm_cam_csi2_clkctrl; | |
01b753ff S |
210 | |
211 | /* cm2.dss */ | |
212 | u32 cm_dss_clkstctrl; | |
213 | u32 cm_dss_dss_clkctrl; | |
214 | ||
215 | /* cm2.sgx */ | |
216 | u32 cm_sgx_clkstctrl; | |
217 | u32 cm_sgx_sgx_clkctrl; | |
218 | ||
219 | /* cm2.l3init */ | |
220 | u32 cm_l3init_clkstctrl; | |
221 | ||
222 | /* cm2.l3init */ | |
223 | u32 cm_l3init_hsmmc1_clkctrl; | |
224 | u32 cm_l3init_hsmmc2_clkctrl; | |
225 | u32 cm_l3init_hsi_clkctrl; | |
226 | u32 cm_l3init_hsusbhost_clkctrl; | |
227 | u32 cm_l3init_hsusbotg_clkctrl; | |
228 | u32 cm_l3init_hsusbtll_clkctrl; | |
229 | u32 cm_l3init_p1500_clkctrl; | |
8ffcf74b | 230 | u32 cm_l3init_sata_clkctrl; |
01b753ff S |
231 | u32 cm_l3init_fsusb_clkctrl; |
232 | u32 cm_l3init_ocp2scp1_clkctrl; | |
d861a333 | 233 | u32 cm_l3init_ocp2scp3_clkctrl; |
d3cfcb3e | 234 | u32 cm_l3init_usb_otg_ss1_clkctrl; |
7beaf8b6 | 235 | u32 cm_l3init_usb_otg_ss2_clkctrl; |
01b753ff | 236 | |
4d0df9c1 AT |
237 | u32 prm_irqstatus_mpu_2; |
238 | ||
01b753ff S |
239 | /* cm2.l4per */ |
240 | u32 cm_l4per_clkstctrl; | |
241 | u32 cm_l4per_dynamicdep; | |
242 | u32 cm_l4per_adc_clkctrl; | |
243 | u32 cm_l4per_gptimer10_clkctrl; | |
244 | u32 cm_l4per_gptimer11_clkctrl; | |
245 | u32 cm_l4per_gptimer2_clkctrl; | |
246 | u32 cm_l4per_gptimer3_clkctrl; | |
247 | u32 cm_l4per_gptimer4_clkctrl; | |
248 | u32 cm_l4per_gptimer9_clkctrl; | |
249 | u32 cm_l4per_elm_clkctrl; | |
250 | u32 cm_l4per_gpio2_clkctrl; | |
251 | u32 cm_l4per_gpio3_clkctrl; | |
252 | u32 cm_l4per_gpio4_clkctrl; | |
253 | u32 cm_l4per_gpio5_clkctrl; | |
254 | u32 cm_l4per_gpio6_clkctrl; | |
255 | u32 cm_l4per_hdq1w_clkctrl; | |
256 | u32 cm_l4per_hecc1_clkctrl; | |
257 | u32 cm_l4per_hecc2_clkctrl; | |
258 | u32 cm_l4per_i2c1_clkctrl; | |
259 | u32 cm_l4per_i2c2_clkctrl; | |
260 | u32 cm_l4per_i2c3_clkctrl; | |
261 | u32 cm_l4per_i2c4_clkctrl; | |
262 | u32 cm_l4per_l4per_clkctrl; | |
263 | u32 cm_l4per_mcasp2_clkctrl; | |
264 | u32 cm_l4per_mcasp3_clkctrl; | |
265 | u32 cm_l4per_mgate_clkctrl; | |
266 | u32 cm_l4per_mcspi1_clkctrl; | |
267 | u32 cm_l4per_mcspi2_clkctrl; | |
268 | u32 cm_l4per_mcspi3_clkctrl; | |
269 | u32 cm_l4per_mcspi4_clkctrl; | |
270 | u32 cm_l4per_gpio7_clkctrl; | |
271 | u32 cm_l4per_gpio8_clkctrl; | |
272 | u32 cm_l4per_mmcsd3_clkctrl; | |
273 | u32 cm_l4per_mmcsd4_clkctrl; | |
274 | u32 cm_l4per_msprohg_clkctrl; | |
275 | u32 cm_l4per_slimbus2_clkctrl; | |
c97a9b32 | 276 | u32 cm_l4per_qspi_clkctrl; |
01b753ff S |
277 | u32 cm_l4per_uart1_clkctrl; |
278 | u32 cm_l4per_uart2_clkctrl; | |
279 | u32 cm_l4per_uart3_clkctrl; | |
280 | u32 cm_l4per_uart4_clkctrl; | |
281 | u32 cm_l4per_mmcsd5_clkctrl; | |
282 | u32 cm_l4per_i2c5_clkctrl; | |
283 | u32 cm_l4per_uart5_clkctrl; | |
284 | u32 cm_l4per_uart6_clkctrl; | |
285 | u32 cm_l4sec_clkstctrl; | |
286 | u32 cm_l4sec_staticdep; | |
287 | u32 cm_l4sec_dynamicdep; | |
288 | u32 cm_l4sec_aes1_clkctrl; | |
289 | u32 cm_l4sec_aes2_clkctrl; | |
290 | u32 cm_l4sec_des3des_clkctrl; | |
291 | u32 cm_l4sec_pkaeip29_clkctrl; | |
292 | u32 cm_l4sec_rng_clkctrl; | |
293 | u32 cm_l4sec_sha2md51_clkctrl; | |
294 | u32 cm_l4sec_cryptodma_clkctrl; | |
295 | ||
296 | /* l4 wkup regs */ | |
297 | u32 cm_abe_pll_ref_clksel; | |
298 | u32 cm_sys_clksel; | |
97405d84 | 299 | u32 cm_abe_pll_sys_clksel; |
01b753ff S |
300 | u32 cm_wkup_clkstctrl; |
301 | u32 cm_wkup_l4wkup_clkctrl; | |
302 | u32 cm_wkup_wdtimer1_clkctrl; | |
303 | u32 cm_wkup_wdtimer2_clkctrl; | |
304 | u32 cm_wkup_gpio1_clkctrl; | |
305 | u32 cm_wkup_gptimer1_clkctrl; | |
306 | u32 cm_wkup_gptimer12_clkctrl; | |
307 | u32 cm_wkup_synctimer_clkctrl; | |
308 | u32 cm_wkup_usim_clkctrl; | |
309 | u32 cm_wkup_sarram_clkctrl; | |
310 | u32 cm_wkup_keyboard_clkctrl; | |
311 | u32 cm_wkup_rtc_clkctrl; | |
312 | u32 cm_wkup_bandgap_clkctrl; | |
313 | u32 cm_wkupaon_scrm_clkctrl; | |
d4d986ee | 314 | u32 cm_wkupaon_io_srcomp_clkctrl; |
d4e4129c LV |
315 | u32 prm_rstctrl; |
316 | u32 prm_rstst; | |
0b1b60c7 | 317 | u32 prm_rsttime; |
eda6fbcc | 318 | u32 prm_io_pmctrl; |
01b753ff S |
319 | u32 prm_vc_val_bypass; |
320 | u32 prm_vc_cfg_i2c_mode; | |
321 | u32 prm_vc_cfg_i2c_clk; | |
4d0df9c1 AT |
322 | u32 prm_abbldo_mpu_setup; |
323 | u32 prm_abbldo_mpu_ctrl; | |
01b753ff S |
324 | |
325 | u32 cm_div_m4_dpll_core; | |
326 | u32 cm_div_m5_dpll_core; | |
327 | u32 cm_div_m6_dpll_core; | |
328 | u32 cm_div_m7_dpll_core; | |
329 | u32 cm_div_m4_dpll_iva; | |
330 | u32 cm_div_m5_dpll_iva; | |
331 | u32 cm_div_m4_dpll_ddrphy; | |
332 | u32 cm_div_m5_dpll_ddrphy; | |
333 | u32 cm_div_m6_dpll_ddrphy; | |
334 | u32 cm_div_m4_dpll_per; | |
335 | u32 cm_div_m5_dpll_per; | |
336 | u32 cm_div_m6_dpll_per; | |
337 | u32 cm_div_m7_dpll_per; | |
338 | u32 cm_l3instr_intrconn_wp1_clkct; | |
339 | u32 cm_l3init_usbphy_clkctrl; | |
340 | u32 cm_l4per_mcbsp4_clkctrl; | |
341 | u32 prm_vc_cfg_channel; | |
ee28edac LP |
342 | |
343 | /* SCRM stuff, used by some boards */ | |
344 | u32 scrm_auxclk0; | |
345 | u32 scrm_auxclk1; | |
f986d972 M |
346 | |
347 | /* GMAC Clk Ctrl */ | |
348 | u32 cm_gmac_gmac_clkctrl; | |
349 | u32 cm_gmac_clkstctrl; | |
37be54fd LV |
350 | |
351 | /* IPU */ | |
352 | u32 cm_ipu_clkstctrl; | |
353 | u32 cm_ipu_i2c5_clkctrl; | |
8a09cfe1 V |
354 | |
355 | /*l3main1 edma*/ | |
356 | u32 cm_l3main1_tptc1_clkctrl; | |
357 | u32 cm_l3main1_tptc2_clkctrl; | |
01b753ff S |
358 | }; |
359 | ||
c43c8339 LV |
360 | struct omap_sys_ctrl_regs { |
361 | u32 control_status; | |
b1e26e3b M |
362 | u32 control_core_mac_id_0_lo; |
363 | u32 control_core_mac_id_0_hi; | |
364 | u32 control_core_mac_id_1_lo; | |
365 | u32 control_core_mac_id_1_hi; | |
4d0df9c1 | 366 | u32 control_std_fuse_opp_vdd_mpu_2; |
d861a333 | 367 | u32 control_phy_power_usb; |
8b12f177 LV |
368 | u32 control_core_mmr_lock1; |
369 | u32 control_core_mmr_lock2; | |
370 | u32 control_core_mmr_lock3; | |
371 | u32 control_core_mmr_lock4; | |
372 | u32 control_core_mmr_lock5; | |
373 | u32 control_core_control_io1; | |
374 | u32 control_core_control_io2; | |
c43c8339 | 375 | u32 control_id_code; |
f12467d1 DK |
376 | u32 control_std_fuse_die_id_0; |
377 | u32 control_std_fuse_die_id_1; | |
378 | u32 control_std_fuse_die_id_2; | |
379 | u32 control_std_fuse_die_id_3; | |
c43c8339 LV |
380 | u32 control_std_fuse_opp_bgap; |
381 | u32 control_ldosram_iva_voltage_ctrl; | |
382 | u32 control_ldosram_mpu_voltage_ctrl; | |
383 | u32 control_ldosram_core_voltage_ctrl; | |
9239f5b6 | 384 | u32 control_usbotghs_ctrl; |
8ffcf74b | 385 | u32 control_phy_power_sata; |
8b12f177 | 386 | u32 control_padconf_core_base; |
c43c8339 LV |
387 | u32 control_paconf_global; |
388 | u32 control_paconf_mode; | |
389 | u32 control_smart1io_padconf_0; | |
390 | u32 control_smart1io_padconf_1; | |
391 | u32 control_smart1io_padconf_2; | |
392 | u32 control_smart2io_padconf_0; | |
393 | u32 control_smart2io_padconf_1; | |
394 | u32 control_smart2io_padconf_2; | |
395 | u32 control_smart3io_padconf_0; | |
396 | u32 control_smart3io_padconf_1; | |
397 | u32 control_pbias; | |
398 | u32 control_i2c_0; | |
399 | u32 control_camera_rx; | |
400 | u32 control_hdmi_tx_phy; | |
401 | u32 control_uniportm; | |
402 | u32 control_dsiphy; | |
403 | u32 control_mcbsplp; | |
404 | u32 control_usb2phycore; | |
405 | u32 control_hdmi_1; | |
406 | u32 control_hsi; | |
407 | u32 control_ddr3ch1_0; | |
408 | u32 control_ddr3ch2_0; | |
409 | u32 control_ddrch1_0; | |
410 | u32 control_ddrch1_1; | |
411 | u32 control_ddrch2_0; | |
412 | u32 control_ddrch2_1; | |
413 | u32 control_lpddr2ch1_0; | |
414 | u32 control_lpddr2ch1_1; | |
415 | u32 control_ddrio_0; | |
416 | u32 control_ddrio_1; | |
417 | u32 control_ddrio_2; | |
92b0482c | 418 | u32 control_ddr_control_ext_0; |
c43c8339 LV |
419 | u32 control_lpddr2io1_0; |
420 | u32 control_lpddr2io1_1; | |
421 | u32 control_lpddr2io1_2; | |
422 | u32 control_lpddr2io1_3; | |
423 | u32 control_lpddr2io2_0; | |
424 | u32 control_lpddr2io2_1; | |
425 | u32 control_lpddr2io2_2; | |
426 | u32 control_lpddr2io2_3; | |
427 | u32 control_hyst_1; | |
428 | u32 control_usbb_hsic_control; | |
429 | u32 control_c2c; | |
430 | u32 control_core_control_spare_rw; | |
431 | u32 control_core_control_spare_r; | |
432 | u32 control_core_control_spare_r_c0; | |
433 | u32 control_srcomp_north_side; | |
434 | u32 control_srcomp_south_side; | |
435 | u32 control_srcomp_east_side; | |
436 | u32 control_srcomp_west_side; | |
437 | u32 control_srcomp_code_latch; | |
438 | u32 control_pbiaslite; | |
439 | u32 control_port_emif1_sdram_config; | |
440 | u32 control_port_emif1_lpddr2_nvm_config; | |
441 | u32 control_port_emif2_sdram_config; | |
442 | u32 control_emif1_sdram_config_ext; | |
443 | u32 control_emif2_sdram_config_ext; | |
4d0df9c1 | 444 | u32 control_wkup_ldovbb_mpu_voltage_ctrl; |
c43c8339 LV |
445 | u32 control_smart1nopmio_padconf_0; |
446 | u32 control_smart1nopmio_padconf_1; | |
447 | u32 control_padconf_mode; | |
448 | u32 control_xtal_oscillator; | |
449 | u32 control_i2c_2; | |
450 | u32 control_ckobuffer; | |
451 | u32 control_wkup_control_spare_rw; | |
452 | u32 control_wkup_control_spare_r; | |
453 | u32 control_wkup_control_spare_r_c0; | |
454 | u32 control_srcomp_east_side_wkup; | |
455 | u32 control_efuse_1; | |
456 | u32 control_efuse_2; | |
457 | u32 control_efuse_3; | |
458 | u32 control_efuse_4; | |
459 | u32 control_efuse_5; | |
460 | u32 control_efuse_6; | |
461 | u32 control_efuse_7; | |
462 | u32 control_efuse_8; | |
463 | u32 control_efuse_9; | |
464 | u32 control_efuse_10; | |
465 | u32 control_efuse_11; | |
466 | u32 control_efuse_12; | |
467 | u32 control_efuse_13; | |
8b12f177 | 468 | u32 control_padconf_wkup_base; |
eda6fbcc LV |
469 | u32 iodelay_config_base; |
470 | u32 ctrl_core_sma_sw_0; | |
76cff2b1 | 471 | u32 ctrl_core_sma_sw_1; |
c43c8339 LV |
472 | }; |
473 | ||
ee9447bf S |
474 | struct dpll_params { |
475 | u32 m; | |
476 | u32 n; | |
477 | s8 m2; | |
478 | s8 m3; | |
479 | s8 m4_h11; | |
480 | s8 m5_h12; | |
481 | s8 m6_h13; | |
482 | s8 m7_h14; | |
47abc3df | 483 | s8 h21; |
ee9447bf S |
484 | s8 h22; |
485 | s8 h23; | |
47abc3df | 486 | s8 h24; |
ee9447bf S |
487 | }; |
488 | ||
489 | struct dpll_regs { | |
490 | u32 cm_clkmode_dpll; | |
491 | u32 cm_idlest_dpll; | |
492 | u32 cm_autoidle_dpll; | |
493 | u32 cm_clksel_dpll; | |
494 | u32 cm_div_m2_dpll; | |
495 | u32 cm_div_m3_dpll; | |
496 | u32 cm_div_m4_h11_dpll; | |
497 | u32 cm_div_m5_h12_dpll; | |
498 | u32 cm_div_m6_h13_dpll; | |
499 | u32 cm_div_m7_h14_dpll; | |
47abc3df S |
500 | u32 reserved[2]; |
501 | u32 cm_div_h21_dpll; | |
ee9447bf S |
502 | u32 cm_div_h22_dpll; |
503 | u32 cm_div_h23_dpll; | |
47abc3df | 504 | u32 cm_div_h24_dpll; |
ee9447bf S |
505 | }; |
506 | ||
507 | struct dplls { | |
508 | const struct dpll_params *mpu; | |
509 | const struct dpll_params *core; | |
510 | const struct dpll_params *per; | |
511 | const struct dpll_params *abe; | |
512 | const struct dpll_params *iva; | |
513 | const struct dpll_params *usb; | |
ea8eff1f | 514 | const struct dpll_params *ddr; |
65e9d56f | 515 | const struct dpll_params *gmac; |
ee9447bf S |
516 | }; |
517 | ||
3fcdd4a5 S |
518 | struct pmic_data { |
519 | u32 base_offset; | |
520 | u32 step; | |
521 | u32 start_code; | |
522 | unsigned gpio; | |
523 | int gpio_en; | |
4ca94d81 LV |
524 | u32 i2c_slave_addr; |
525 | void (*pmic_bus_init)(void); | |
526 | int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); | |
3fcdd4a5 S |
527 | }; |
528 | ||
18c9d55a NM |
529 | /** |
530 | * struct volts_efuse_data - efuse definition for voltage | |
531 | * @reg: register address for efuse | |
532 | * @reg_bits: Number of bits in a register address, mandatory. | |
533 | */ | |
534 | struct volts_efuse_data { | |
535 | u32 reg; | |
536 | u8 reg_bits; | |
3fcdd4a5 S |
537 | }; |
538 | ||
539 | struct volts { | |
540 | u32 value; | |
541 | u32 addr; | |
18c9d55a | 542 | struct volts_efuse_data efuse; |
3fcdd4a5 S |
543 | struct pmic_data *pmic; |
544 | }; | |
545 | ||
546 | struct vcores_data { | |
547 | struct volts mpu; | |
548 | struct volts core; | |
549 | struct volts mm; | |
63fc0c77 LV |
550 | struct volts gpu; |
551 | struct volts eve; | |
552 | struct volts iva; | |
3fcdd4a5 S |
553 | }; |
554 | ||
01b753ff S |
555 | extern struct prcm_regs const **prcm; |
556 | extern struct prcm_regs const omap5_es1_prcm; | |
afc2f9dc | 557 | extern struct prcm_regs const omap5_es2_prcm; |
01b753ff | 558 | extern struct prcm_regs const omap4_prcm; |
d4e4129c | 559 | extern struct prcm_regs const dra7xx_prcm; |
ee9447bf | 560 | extern struct dplls const **dplls_data; |
56fe4055 | 561 | extern struct dplls dra7xx_dplls; |
3fcdd4a5 | 562 | extern struct vcores_data const **omap_vcores; |
ee9447bf | 563 | extern const u32 sys_clk_array[8]; |
c43c8339 LV |
564 | extern struct omap_sys_ctrl_regs const **ctrl; |
565 | extern struct omap_sys_ctrl_regs const omap4_ctrl; | |
566 | extern struct omap_sys_ctrl_regs const omap5_ctrl; | |
8b12f177 | 567 | extern struct omap_sys_ctrl_regs const dra7xx_ctrl; |
01b753ff | 568 | |
56fe4055 FB |
569 | extern struct pmic_data tps659038; |
570 | ||
01b753ff | 571 | void hw_data_init(void); |
ee9447bf S |
572 | |
573 | const struct dpll_params *get_mpu_dpll_params(struct dplls const *); | |
574 | const struct dpll_params *get_core_dpll_params(struct dplls const *); | |
575 | const struct dpll_params *get_per_dpll_params(struct dplls const *); | |
576 | const struct dpll_params *get_iva_dpll_params(struct dplls const *); | |
577 | const struct dpll_params *get_usb_dpll_params(struct dplls const *); | |
578 | const struct dpll_params *get_abe_dpll_params(struct dplls const *); | |
579 | ||
580 | void do_enable_clocks(u32 const *clk_domains, | |
581 | u32 const *clk_modules_hw_auto, | |
582 | u32 const *clk_modules_explicit_en, | |
583 | u8 wait_for_enable); | |
584 | ||
16ca1d09 KVA |
585 | void do_disable_clocks(u32 const *clk_domains, |
586 | u32 const *clk_modules_disable, | |
587 | u8 wait_for_disable); | |
588 | ||
ee9447bf S |
589 | void setup_post_dividers(u32 const base, |
590 | const struct dpll_params *params); | |
591 | u32 omap_ddr_clk(void); | |
592 | u32 get_sys_clk_index(void); | |
593 | void enable_basic_clocks(void); | |
594 | void enable_basic_uboot_clocks(void); | |
3fcdd4a5 S |
595 | void scale_vcores(struct vcores_data const *); |
596 | u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); | |
597 | void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); | |
4d0df9c1 AT |
598 | void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, |
599 | u32 txdone, u32 txdone_mask, u32 opp); | |
600 | s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); | |
3776801d | 601 | |
8a0c6d6f | 602 | void usb_fake_mac_from_die_id(u32 *id); |
f12467d1 | 603 | void usb_set_serial_num_from_die_id(u32 *id); |
eda6fbcc | 604 | void recalibrate_iodelay(void); |
8a0c6d6f | 605 | |
6d8abe6a NM |
606 | void omap_smc1(u32 service, u32 val); |
607 | ||
8a09cfe1 V |
608 | void enable_edma3_clocks(void); |
609 | void disable_edma3_clocks(void); | |
610 | ||
4d0df9c1 AT |
611 | /* ABB */ |
612 | #define OMAP_ABB_NOMINAL_OPP 0 | |
613 | #define OMAP_ABB_FAST_OPP 1 | |
614 | #define OMAP_ABB_SLOW_OPP 3 | |
615 | #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0) | |
616 | #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1) | |
617 | #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2) | |
618 | #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6) | |
619 | #define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0) | |
620 | #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2) | |
621 | #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1) | |
622 | #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8) | |
623 | ||
087189fb S |
624 | static inline u32 omap_revision(void) |
625 | { | |
626 | extern u32 *const omap_si_rev; | |
627 | return *omap_si_rev; | |
628 | } | |
e9d6cd04 | 629 | |
8c16dd6f RN |
630 | #define OMAP44xx 0x44000000 |
631 | ||
632 | static inline u8 is_omap44xx(void) | |
633 | { | |
634 | extern u32 *const omap_si_rev; | |
635 | return (*omap_si_rev & 0xFF000000) == OMAP44xx; | |
636 | }; | |
637 | ||
e9d6cd04 LV |
638 | #define OMAP54xx 0x54000000 |
639 | ||
640 | static inline u8 is_omap54xx(void) | |
641 | { | |
642 | extern u32 *const omap_si_rev; | |
643 | return ((*omap_si_rev & 0xFF000000) == OMAP54xx); | |
644 | } | |
39302dcd S |
645 | |
646 | #define DRA7XX 0x07000000 | |
c7400e48 | 647 | #define DRA72X 0x07200000 |
39302dcd S |
648 | |
649 | static inline u8 is_dra7xx(void) | |
650 | { | |
651 | extern u32 *const omap_si_rev; | |
652 | return ((*omap_si_rev & 0xFF000000) == DRA7XX); | |
653 | } | |
c7400e48 LV |
654 | |
655 | static inline u8 is_dra72x(void) | |
656 | { | |
657 | extern u32 *const omap_si_rev; | |
658 | return (*omap_si_rev & 0xFFF00000) == DRA72X; | |
659 | } | |
4a0eb757 | 660 | #endif |
087189fb | 661 | |
508a58fa S |
662 | /* |
663 | * silicon revisions. | |
664 | * Moving this to common, so that most of code can be moved to common, | |
665 | * directories. | |
666 | */ | |
667 | ||
668 | /* omap4 */ | |
669 | #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF | |
670 | #define OMAP4430_ES1_0 0x44300100 | |
671 | #define OMAP4430_ES2_0 0x44300200 | |
672 | #define OMAP4430_ES2_1 0x44300210 | |
673 | #define OMAP4430_ES2_2 0x44300220 | |
674 | #define OMAP4430_ES2_3 0x44300230 | |
675 | #define OMAP4460_ES1_0 0x44600100 | |
9404758e | 676 | #define OMAP4460_ES1_1 0x44600110 |
696f81f9 | 677 | #define OMAP4470_ES1_0 0x44700100 |
508a58fa S |
678 | |
679 | /* omap5 */ | |
680 | #define OMAP5430_SILICON_ID_INVALID 0 | |
681 | #define OMAP5430_ES1_0 0x54300100 | |
0a0bf7b2 | 682 | #define OMAP5432_ES1_0 0x54320100 |
eed7c0f7 S |
683 | #define OMAP5430_ES2_0 0x54300200 |
684 | #define OMAP5432_ES2_0 0x54320200 | |
de62688b LV |
685 | |
686 | /* DRA7XX */ | |
687 | #define DRA752_ES1_0 0x07520100 | |
3ac8c0bf | 688 | #define DRA752_ES1_1 0x07520110 |
c1ea3bec | 689 | #define DRA752_ES2_0 0x07520200 |
ee77a238 | 690 | #define DRA722_ES1_0 0x07220100 |
f92f2277 S |
691 | |
692 | /* | |
693 | * SRAM scratch space entries | |
694 | */ | |
f92f2277 S |
695 | #define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR |
696 | #define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) | |
697 | #define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) | |
698 | #define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) | |
699 | #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) | |
700 | #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) | |
701 | #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) | |
702 | #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) | |
fda06812 S |
703 | #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) |
704 | #define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28) | |
705 | ||
60c7c30a PK |
706 | /* Boot parameters */ |
707 | #define DEVICE_DATA_OFFSET 0x18 | |
708 | #define BOOT_MODE_OFFSET 0x8 | |
709 | ||
710 | #define CH_FLAGS_CHSETTINGS (1 << 0) | |
711 | #define CH_FLAGS_CHRAM (1 << 1) | |
712 | #define CH_FLAGS_CHFLASH (1 << 2) | |
713 | #define CH_FLAGS_CHMMCSD (1 << 3) | |
714 | ||
ed19bdae PK |
715 | #ifndef __ASSEMBLY__ |
716 | u32 omap_sys_boot_device(void); | |
717 | #endif | |
718 | ||
d2f18c27 | 719 | #endif /* _OMAP_COMMON_H_ */ |