[people/ms/u-boot.git] / arch / arm / include / asm / system.h

#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H

#ifdef CONFIG_ARM64

/*
 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
 */
#define CR_M		(1 << 0)	/* MMU enable			*/
#define CR_A		(1 << 1)	/* Alignment abort enable	*/
#define CR_C		(1 << 2)	/* Dcache enable		*/
#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
#define CR_I		(1 << 12)	/* Icache enable		*/
#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/

#define PGTABLE_SIZE	(0x10000)

#ifndef __ASSEMBLY__

#define isb()				\
	({asm volatile(			\
	"isb" : : : "memory");		\
	})

#define wfi()				\
	({asm volatile(			\
	"wfi" : : : "memory");		\
	})

static inline unsigned int current_el(void)
{
	unsigned int el;
	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
	return el >> 2;
}

static inline unsigned int get_sctlr(void)
{
	unsigned int el, val;

	el = current_el();
	if (el == 1)
		asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
	else if (el == 2)
		asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
	else
		asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");

	return val;
}

static inline void set_sctlr(unsigned int val)
{
	unsigned int el;

	el = current_el();
	if (el == 1)
		asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
	else if (el == 2)
		asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
	else
		asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");

	asm volatile("isb");
}

void __asm_flush_dcache_all(void);
void __asm_invalidate_dcache_all(void);
void __asm_flush_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);

void armv8_switch_to_el2(void);
void armv8_switch_to_el1(void);
void gic_init(void);
void gic_send_sgi(unsigned long sgino);
void wait_for_wakeup(void);
void smp_kick_all_cpus(void);

void flush_l3_cache(void);

#endif	/* __ASSEMBLY__ */

#else /* CONFIG_ARM64 */

#ifdef __KERNEL__

#define CPU_ARCH_UNKNOWN	0
#define CPU_ARCH_ARMv3		1
#define CPU_ARCH_ARMv4		2
#define CPU_ARCH_ARMv4T		3
#define CPU_ARCH_ARMv5		4
#define CPU_ARCH_ARMv5T		5
#define CPU_ARCH_ARMv5TE	6
#define CPU_ARCH_ARMv5TEJ	7
#define CPU_ARCH_ARMv6		8
#define CPU_ARCH_ARMv7		9

/*
 * CR1 bits (CP#15 CR1)
 */
#define CR_M	(1 << 0)	/* MMU enable				*/
#define CR_A	(1 << 1)	/* Alignment abort enable		*/
#define CR_C	(1 << 2)	/* Dcache enable			*/
#define CR_W	(1 << 3)	/* Write buffer enable			*/
#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
#define CR_D	(1 << 5)	/* 32-bit data address range		*/
#define CR_L	(1 << 6)	/* Implementation defined		*/
#define CR_B	(1 << 7)	/* Big endian				*/
#define CR_S	(1 << 8)	/* System MMU protection		*/
#define CR_R	(1 << 9)	/* ROM MMU protection			*/
#define CR_F	(1 << 10)	/* Implementation defined		*/
#define CR_Z	(1 << 11)	/* Implementation defined		*/
#define CR_I	(1 << 12)	/* Icache enable			*/
#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
#define CR_DT	(1 << 16)
#define CR_IT	(1 << 18)
#define CR_ST	(1 << 19)
#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
#define CR_U	(1 << 22)	/* Unaligned access operation		*/
#define CR_XP	(1 << 23)	/* Extended page tables			*/
#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
#define CR_AFE	(1 << 29)	/* Access flag enable			*/
#define CR_TE	(1 << 30)	/* Thumb exception enable		*/

#define PGTABLE_SIZE		(4096 * 4)

/*
 * This is used to ensure the compiler did actually allocate the register we
 * asked it for some inline assembly sequences.  Apparently we can't trust
 * the compiler from one version to another so a bit of paranoia won't hurt.
 * This string is meant to be concatenated with the inline asm string and
 * will cause compilation to stop on mismatch.
 * (for details, see gcc PR 15089)
 */
#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"

#ifndef __ASSEMBLY__

#define isb() __asm__ __volatile__ ("" : : : "memory")

#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");

#ifdef __ARM_ARCH_7A__
#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
#else
#define wfi()
#endif

static inline unsigned int get_cr(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
	return val;
}

static inline void set_cr(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
	  : : "r" (val) : "cc");
	isb();
}

static inline unsigned int get_dacr(void)
{
	unsigned int val;
	asm("mrc p15, 0, %0, c3, c0, 0	@ get DACR" : "=r" (val) : : "cc");
	return val;
}

static inline void set_dacr(unsigned int val)
{
	asm volatile("mcr p15, 0, %0, c3, c0, 0	@ set DACR"
	  : : "r" (val) : "cc");
	isb();
}

/* options available for data cache on each page */
enum dcache_option {
	DCACHE_OFF = 0x12,
	DCACHE_WRITETHROUGH = 0x1a,
	DCACHE_WRITEBACK = 0x1e,
	DCACHE_WRITEALLOC = 0x16,
};

/* Size of an MMU section */
enum {
	MMU_SECTION_SHIFT	= 20,
	MMU_SECTION_SIZE	= 1 << MMU_SECTION_SHIFT,
};

/**
 * Change the cache settings for a region.
 *
 * \param start		start address of memory region to change
 * \param size		size of memory region to change
 * \param option	dcache option to select
 */
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
				     enum dcache_option option);

/**
 * Register an update to the page tables, and flush the TLB
 *
 * \param start		start address of update in page table
 * \param stop		stop address of update in page table
 */
void mmu_page_table_flush(unsigned long start, unsigned long stop);

#ifdef CONFIG_SYS_NONCACHED_MEMORY
void noncached_init(void);
phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* CONFIG_SYS_NONCACHED_MEMORY */

#endif /* __ASSEMBLY__ */

#define arch_align_stack(x) (x)

#endif /* __KERNEL__ */

#endif /* CONFIG_ARM64 */

#endif
Commit	Line	Data
677e62f4 JCPV	1	#ifndef __ASM_ARM_SYSTEM_H
	2	#define __ASM_ARM_SYSTEM_H
	3
0ae76531 DF	4	#ifdef CONFIG_ARM64
	5
	6	/*
	7	* SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
	8	*/
	9	#define CR_M (1 << 0) /* MMU enable */
	10	#define CR_A (1 << 1) /* Alignment abort enable */
	11	#define CR_C (1 << 2) /* Dcache enable */
	12	#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
	13	#define CR_I (1 << 12) /* Icache enable */
	14	#define CR_WXN (1 << 19) /* Write Permision Imply XN */
	15	#define CR_EE (1 << 25) /* Exception (Big) Endian */
	16
	17	#define PGTABLE_SIZE (0x10000)
	18
	19	#ifndef __ASSEMBLY__
	20
	21	#define isb() \
	22	({asm volatile( \
	23	"isb" : : : "memory"); \
	24	})
	25
	26	#define wfi() \
	27	({asm volatile( \
	28	"wfi" : : : "memory"); \
	29	})
	30
	31	static inline unsigned int current_el(void)
	32	{
	33	unsigned int el;
	34	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
	35	return el >> 2;
	36	}
	37
	38	static inline unsigned int get_sctlr(void)
	39	{
	40	unsigned int el, val;
	41
	42	el = current_el();
	43	if (el == 1)
	44	asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
	45	else if (el == 2)
	46	asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
	47	else
	48	asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
	49
	50	return val;
	51	}
	52
	53	static inline void set_sctlr(unsigned int val)
	54	{
	55	unsigned int el;
	56
	57	el = current_el();
	58	if (el == 1)
	59	asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
	60	else if (el == 2)
	61	asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
	62	else
	63	asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
	64
	65	asm volatile("isb");
	66	}
	67
68	void __asm_flush_dcache_all(void);
1e6ad55c	69	void __asm_invalidate_dcache_all(void);
0ae76531 DF	70	void __asm_flush_dcache_range(u64 start, u64 end);
	71	void __asm_invalidate_tlb_all(void);
	72	void __asm_invalidate_icache_all(void);
	73
	74	void armv8_switch_to_el2(void);
	75	void armv8_switch_to_el1(void);
	76	void gic_init(void);
	77	void gic_send_sgi(unsigned long sgino);
	78	void wait_for_wakeup(void);
	79	void smp_kick_all_cpus(void);
	80
2f78eae5 YS	81	void flush_l3_cache(void);
2f78eae5 YS	82
0ae76531 DF	83	#endif /* __ASSEMBLY__ */
	84
	85	#else /* CONFIG_ARM64 */
	86
677e62f4 JCPV	87	#ifdef __KERNEL__
	88
	89	#define CPU_ARCH_UNKNOWN 0
	90	#define CPU_ARCH_ARMv3 1
	91	#define CPU_ARCH_ARMv4 2
	92	#define CPU_ARCH_ARMv4T 3
	93	#define CPU_ARCH_ARMv5 4
	94	#define CPU_ARCH_ARMv5T 5
	95	#define CPU_ARCH_ARMv5TE 6
	96	#define CPU_ARCH_ARMv5TEJ 7
	97	#define CPU_ARCH_ARMv6 8
	98	#define CPU_ARCH_ARMv7 9
	99
	100	/*
	101	* CR1 bits (CP#15 CR1)
	102	*/
	103	#define CR_M (1 << 0) /* MMU enable */
	104	#define CR_A (1 << 1) /* Alignment abort enable */
	105	#define CR_C (1 << 2) /* Dcache enable */
	106	#define CR_W (1 << 3) /* Write buffer enable */
	107	#define CR_P (1 << 4) /* 32-bit exception handler */
	108	#define CR_D (1 << 5) /* 32-bit data address range */
	109	#define CR_L (1 << 6) /* Implementation defined */
	110	#define CR_B (1 << 7) /* Big endian */
	111	#define CR_S (1 << 8) /* System MMU protection */
	112	#define CR_R (1 << 9) /* ROM MMU protection */
	113	#define CR_F (1 << 10) /* Implementation defined */
	114	#define CR_Z (1 << 11) /* Implementation defined */
	115	#define CR_I (1 << 12) /* Icache enable */
	116	#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
	117	#define CR_RR (1 << 14) /* Round Robin cache replacement */
	118	#define CR_L4 (1 << 15) /* LDR pc can set T bit */
	119	#define CR_DT (1 << 16)
	120	#define CR_IT (1 << 18)
	121	#define CR_ST (1 << 19)
	122	#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
	123	#define CR_U (1 << 22) /* Unaligned access operation */
	124	#define CR_XP (1 << 23) /* Extended page tables */
	125	#define CR_VE (1 << 24) /* Vectored interrupts */
	126	#define CR_EE (1 << 25) /* Exception (Big) Endian */
	127	#define CR_TRE (1 << 28) /* TEX remap enable */
	128	#define CR_AFE (1 << 29) /* Access flag enable */
	129	#define CR_TE (1 << 30) /* Thumb exception enable */
	130
0ae76531 DF	131	#define PGTABLE_SIZE (4096 * 4)
0ae76531 DF	132
677e62f4 JCPV	133	/*
	134	* This is used to ensure the compiler did actually allocate the register we
	135	* asked it for some inline assembly sequences. Apparently we can't trust
	136	* the compiler from one version to another so a bit of paranoia won't hurt.
	137	* This string is meant to be concatenated with the inline asm string and
	138	* will cause compilation to stop on mismatch.
	139	* (for details, see gcc PR 15089)
	140	*/
	141	#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
	142
	143	#ifndef __ASSEMBLY__
	144
	145	#define isb() __asm__ __volatile__ ("" : : : "memory")
	146
	147	#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
	148
2ff467c0 RH	149	#ifdef __ARM_ARCH_7A__
	150	#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
	151	#else
	152	#define wfi()
	153	#endif
	154
677e62f4 JCPV	155	static inline unsigned int get_cr(void)
	156	{
	157	unsigned int val;
	158	asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
	159	return val;
	160	}
	161
	162	static inline void set_cr(unsigned int val)
	163	{
	164	asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
	165	: : "r" (val) : "cc");
	166	isb();
	167	}
	168
de63ac27 S	169	static inline unsigned int get_dacr(void)
	170	{
	171	unsigned int val;
	172	asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
	173	return val;
	174	}
	175
	176	static inline void set_dacr(unsigned int val)
	177	{
	178	asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
	179	: : "r" (val) : "cc");
	180	isb();
	181	}
	182
0dde7f53 SG	183	/* options available for data cache on each page */
	184	enum dcache_option {
	185	DCACHE_OFF = 0x12,
	186	DCACHE_WRITETHROUGH = 0x1a,
	187	DCACHE_WRITEBACK = 0x1e,
ff7e9700	188	DCACHE_WRITEALLOC = 0x16,
0dde7f53 SG	189	};
	190
	191	/* Size of an MMU section */
	192	enum {
	193	MMU_SECTION_SHIFT = 20,
	194	MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
	195	};
	196
	197	/**
	198	* Change the cache settings for a region.
	199	*
	200	* \param start start address of memory region to change
	201	* \param size size of memory region to change
	202	* \param option dcache option to select
	203	*/
25026fa9	204	void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
0dde7f53 SG	205	enum dcache_option option);
	206
	207	/**
	208	* Register an update to the page tables, and flush the TLB
	209	*
	210	* \param start start address of update in page table
	211	* \param stop stop address of update in page table
	212	*/
	213	void mmu_page_table_flush(unsigned long start, unsigned long stop);
	214
1dfdd9ba TR	215	#ifdef CONFIG_SYS_NONCACHED_MEMORY
	216	void noncached_init(void);
	217	phys_addr_t noncached_alloc(size_t size, size_t align);
	218	#endif /* CONFIG_SYS_NONCACHED_MEMORY */
	219
677e62f4 JCPV	220	#endif /* __ASSEMBLY__ */
	221
	222	#define arch_align_stack(x) (x)
	223
	224	#endif /* __KERNEL__ */
	225
0ae76531 DF	226	#endif /* CONFIG_ARM64 */
0ae76531 DF	227
677e62f4	228	#endif