[people/ms/u-boot.git] / arch / arm / include / asm / ti-common / davinci_nand.h

/*
 * NAND Flash Driver
 *
 * Copyright (C) 2006-2014 Texas Instruments.
 *
 * Based on Linux DaVinci NAND driver by TI.
 */

#ifndef _DAVINCI_NAND_H_
#define _DAVINCI_NAND_H_

#include <linux/mtd/rawnand.h>
#include <asm/arch/hardware.h>

#define NAND_READ_START  	0x00
#define NAND_READ_END    	0x30
#define NAND_STATUS      	0x70

#define MASK_CLE		0x10
#define MASK_ALE		0x08

#ifdef CONFIG_SYS_NAND_MASK_CLE
#undef MASK_CLE
#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
#endif
#ifdef CONFIG_SYS_NAND_MASK_ALE
#undef MASK_ALE
#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
#endif

struct davinci_emif_regs {
	uint32_t	ercsr;
	uint32_t	awccr;
	uint32_t	sdbcr;
	uint32_t	sdrcr;
	union {
		uint32_t abncr[4];
		struct {
			uint32_t ab1cr;
			uint32_t ab2cr;
			uint32_t ab3cr;
			uint32_t ab4cr;
		};
	};
	uint32_t	sdtimr;
	uint32_t	ddrsr;
	uint32_t	ddrphycr;
	uint32_t	ddrphysr;
	uint32_t	totar;
	uint32_t	totactr;
	uint32_t	ddrphyid_rev;
	uint32_t	sdsretr;
	uint32_t	eirr;
	uint32_t	eimr;
	uint32_t	eimsr;
	uint32_t	eimcr;
	uint32_t	ioctrlr;
	uint32_t	iostatr;
	uint32_t	rsvd0;
	uint32_t	one_nand_cr;
	uint32_t	nandfcr;
	uint32_t	nandfsr;
	uint32_t	rsvd1[2];
	uint32_t	nandfecc[4];
	uint32_t	rsvd2[15];
	uint32_t	nand4biteccload;
	uint32_t	nand4bitecc[4];
	uint32_t	nanderradd1;
	uint32_t	nanderradd2;
	uint32_t	nanderrval1;
	uint32_t	nanderrval2;
};

#define davinci_emif_regs \
	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)

#define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << ((n) - 2))
#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			(((n) - 2) << 4)
#define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + ((n) - 2)))
#define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
#define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
#define DAVINCI_NANDFCR_CS2NAND				(1 << 0)

/* Chip Select setup */
#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
#define DAVINCI_ABCR_WSETUP(n)				(n << 26)
#define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
#define DAVINCI_ABCR_WHOLD(n)				(n << 17)
#define DAVINCI_ABCR_RSETUP(n)				(n << 13)
#define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
#define DAVINCI_ABCR_RHOLD(n)				(n << 4)
#define DAVINCI_ABCR_TA(n)				(n << 2)
#define DAVINCI_ABCR_ASIZE_16BIT			1
#define DAVINCI_ABCR_ASIZE_8BIT				0

void davinci_nand_init(struct nand_chip *nand);

#endif
Commit	Line	Data
ef509b90	1	/*
3e01ed00	2	* NAND Flash Driver
ef509b90	3	*
3e01ed00	4	* Copyright (C) 2006-2014 Texas Instruments.
ef509b90	5	*
3e01ed00	6	* Based on Linux DaVinci NAND driver by TI.
ef509b90	7	*/
ef509b90	8
3e01ed00 KI	9	#ifndef _DAVINCI_NAND_H_
	10	#define _DAVINCI_NAND_H_
	11
6ae3900a	12	#include <linux/mtd/rawnand.h>
ef509b90 VA	13	#include <asm/arch/hardware.h>
ef509b90 VA	14
3e01ed00 KI	15	#define NAND_READ_START 0x00
	16	#define NAND_READ_END 0x30
	17	#define NAND_STATUS 0x70
	18
	19	#define MASK_CLE 0x10
	20	#define MASK_ALE 0x08
	21
	22	#ifdef CONFIG_SYS_NAND_MASK_CLE
	23	#undef MASK_CLE
	24	#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
	25	#endif
	26	#ifdef CONFIG_SYS_NAND_MASK_ALE
	27	#undef MASK_ALE
	28	#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
	29	#endif
	30
ef509b90 VA	31	struct davinci_emif_regs {
	32	uint32_t ercsr;
	33	uint32_t awccr;
	34	uint32_t sdbcr;
	35	uint32_t sdrcr;
3e01ed00 KI	36	union {
3e01ed00 KI	37	uint32_t abncr[4];
c1659942 PH	38	struct {
	39	uint32_t ab1cr;
	40	uint32_t ab2cr;
	41	uint32_t ab3cr;
	42	uint32_t ab4cr;
	43	};
3e01ed00	44	};
ef509b90 VA	45	uint32_t sdtimr;
	46	uint32_t ddrsr;
	47	uint32_t ddrphycr;
	48	uint32_t ddrphysr;
	49	uint32_t totar;
	50	uint32_t totactr;
	51	uint32_t ddrphyid_rev;
	52	uint32_t sdsretr;
	53	uint32_t eirr;
	54	uint32_t eimr;
	55	uint32_t eimsr;
	56	uint32_t eimcr;
	57	uint32_t ioctrlr;
	58	uint32_t iostatr;
	59	uint32_t rsvd0;
	60	uint32_t one_nand_cr;
	61	uint32_t nandfcr;
	62	uint32_t nandfsr;
	63	uint32_t rsvd1[2];
	64	uint32_t nandfecc[4];
	65	uint32_t rsvd2[15];
	66	uint32_t nand4biteccload;
	67	uint32_t nand4bitecc[4];
	68	uint32_t nanderradd1;
	69	uint32_t nanderradd2;
	70	uint32_t nanderrval1;
	71	uint32_t nanderrval2;
	72	};
	73
	74	#define davinci_emif_regs \
	75	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
	76
	77	#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
	78	#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
	79	#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
	80	#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
	81	#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
	82	#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
3e01ed00	83	#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
ef509b90 VA	84
	85	/* Chip Select setup */
	86	#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
	87	#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
3e01ed00 KI	88	#define DAVINCI_ABCR_WSETUP(n) (n << 26)
	89	#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
	90	#define DAVINCI_ABCR_WHOLD(n) (n << 17)
	91	#define DAVINCI_ABCR_RSETUP(n) (n << 13)
	92	#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
	93	#define DAVINCI_ABCR_RHOLD(n) (n << 4)
	94	#define DAVINCI_ABCR_TA(n) (n << 2)
ef509b90 VA	95	#define DAVINCI_ABCR_ASIZE_16BIT 1
	96	#define DAVINCI_ABCR_ASIZE_8BIT 0
	97
3e01ed00 KI	98	void davinci_nand_init(struct nand_chip *nand);
3e01ed00 KI	99
ef509b90	100	#endif