[people/ms/u-boot.git] / arch / arm / lib / asm-offsets.c

/*
 * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
 *
 * This program is used to generate definitions needed by
 * assembly language modules.
 *
 * We use the technique used in the OSF Mach kernel code:
 * generate asm statements containing #defines,
 * compile this file to assembler, and then extract the
 * #defines from the assembly-language output.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/kbuild.h>
#include <linux/arm-smccc.h>

#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
	|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif

int main(void)
{
	/*
	 * TODO : Check if each entry in this file is really necessary.
	 *   - struct esdramc_regs
	 *   - struct max_regs
	 *   - struct aips_regs
	 *   - struct aipi_regs
	 *   - struct clkctl
	 *   - struct dpll
	 * are used only for generating asm-offsets.h.
	 * It means their offset addresses are referenced only from assembly
	 * code. Is it better to define the macros directly in headers?
	 */

#if defined(CONFIG_MX25)
	/* Clock Control Module */
	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));

	/* Enhanced SDRAM Controller */
	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));

	/* Multi-Layer AHB Crossbar Switch */
	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));

	/* AHB <-> IP-Bus Interface */
	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
#endif

#if defined(CONFIG_MX27)
	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));

	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));

	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));

	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
		offsetof(struct system_control_regs, gpcr));
	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
		offsetof(struct system_control_regs, fmcr));
#endif

#if defined(CONFIG_MX35)
	/* Round up to make sure size gives nice stack alignment */
	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));

	/* Multi-Layer AHB Crossbar Switch */
	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));

	/* AHB <-> IP-Bus Interface */
	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
#endif

#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
	/* Round up to make sure size gives nice stack alignment */
	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
#if defined(CONFIG_MX53)
	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
#endif

	/* DPLL */
	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
#endif

#ifdef CONFIG_ARM_SMCCC
	DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
	DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
	DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
	DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
#endif

	return 0;
}
Commit	Line	Data
254d68b6 MY	1	/*
	2	* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
	3	*
	4	* This program is used to generate definitions needed by
	5	* assembly language modules.
	6	*
	7	* We use the technique used in the OSF Mach kernel code:
	8	* generate asm statements containing #defines,
	9	* compile this file to assembler, and then extract the
	10	* #defines from the assembly-language output.
	11	*
	12	* SPDX-License-Identifier: GPL-2.0+
	13	*/
	14
	15	#include <common.h>
	16	#include <linux/kbuild.h>
c54bcf68	17	#include <linux/arm-smccc.h>
254d68b6	18
254d68b6 MY	19	#if defined(CONFIG_MX25) \|\| defined(CONFIG_MX27) \|\| defined(CONFIG_MX35) \
	20	\|\| defined(CONFIG_MX51) \|\| defined(CONFIG_MX53)
	21	#include <asm/arch/imx-regs.h>
	22	#endif
	23
	24	int main(void)
	25	{
	26	/*
	27	* TODO : Check if each entry in this file is really necessary.
254d68b6 MY	28	* - struct esdramc_regs
	29	* - struct max_regs
	30	* - struct aips_regs
	31	* - struct aipi_regs
	32	* - struct clkctl
	33	* - struct dpll
	34	* are used only for generating asm-offsets.h.
	35	* It means their offset addresses are referenced only from assembly
	36	* code. Is it better to define the macros directly in headers?
	37	*/
	38
254d68b6 MY	39	#if defined(CONFIG_MX25)
	40	/* Clock Control Module */
	41	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
	42	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
	43	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
	44	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
	45	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
	46	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
	47
	48	/* Enhanced SDRAM Controller */
	49	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
	50	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
	51	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
	52
	53	/* Multi-Layer AHB Crossbar Switch */
	54	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
	55	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
	56	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
	57	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
	58	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
	59	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
	60	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
	61	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
	62	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
	63	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
	64	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
	65	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
	66	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
	67	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
	68	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
	69
	70	/* AHB <-> IP-Bus Interface */
	71	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
	72	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
	73	#endif
	74
	75	#if defined(CONFIG_MX27)
	76	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
	77	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
	78	DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
	79	DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
	80
	81	DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
	82	DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
	83	DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
	84	DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
	85	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
	86	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
	87	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
	88
	89	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
	90	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
	91	DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
	92	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
	93	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
	94
	95	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
	96	offsetof(struct system_control_regs, gpcr));
	97	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
	98	offsetof(struct system_control_regs, fmcr));
	99	#endif
	100
	101	#if defined(CONFIG_MX35)
	102	/* Round up to make sure size gives nice stack alignment */
103	DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
104	DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
105	DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
106	DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
107	DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
108	DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
109	DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
110	DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
111	DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
112	DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
113	DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
114	DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
115	DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
116	DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
117	DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
118
119	/* Multi-Layer AHB Crossbar Switch */
120	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
121	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
122	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
123	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
124	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
125	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
126	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
127	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
128	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
129	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
130	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
131	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
132	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
133	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
134	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
135	DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
136
137	/* AHB <-> IP-Bus Interface */
138	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
139	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
140	DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
141	DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
142	DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
143	DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
144	DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
145	DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
146	DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
147	DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
148	DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
149	#endif
150
151	#if defined(CONFIG_MX51) \|\| defined(CONFIG_MX53)
152	/* Round up to make sure size gives nice stack alignment */
153	DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
154	DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
155	DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
156	DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
157	DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
158	DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
159	DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
160	DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
161	DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
162	DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
163	DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
164	DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
165	DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
166	DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
167	DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
168	DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
169	DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
170	DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
171	DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
172	DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
173	DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
174	DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
175	DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
176	DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
177	DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
178	DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
179	DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
180	DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
181	DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
182	DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
183	DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
184	DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
185	DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
186	DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
187	#if defined(CONFIG_MX53)
188	DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
189	#endif
190
191	/* DPLL */
192	DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
193	DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
194	DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
195	DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
196	DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
197	DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
198	DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
199	DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
200	#endif
201
c54bcf68 MY	202	#ifdef CONFIG_ARM_SMCCC
	203	DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
	204	DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
	205	DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
	206	DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
	207	#endif
	208
254d68b6 MY	209	return 0;
254d68b6 MY	210	}