[people/ms/u-boot.git] / arch / arm / mach-at91 / arm926ejs / timer.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pit.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <div64.h>

#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif

DECLARE_GLOBAL_DATA_PTR;

/*
 * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
 * setting the 20 bit counter period to its maximum (0xfffff).
 * (See the relevant data sheets to understand that this really works)
 *
 * We do also mimic the typical powerpc way of incrementing
 * two 32 bit registers called tbl and tbu.
 *
 * Those registers increment at 1/16 the main clock rate.
 */

#define TIMER_LOAD_VAL	0xfffff

/*
 * Use the PITC in full 32 bit incrementing mode
 */
int timer_init(void)
{
	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
	at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;

	/* Enable PITC Clock */
	writel(1 << ATMEL_ID_SYS, &pmc->pcer);

	/* Enable PITC */
	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);

	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;

	return 0;
}

/*
 * Return the number of timer ticks per second.
 */
ulong get_tbclk(void)
{
	return gd->arch.timer_rate_hz;
}
Commit	Line	Data
fefb6c10 SP	1	/*
fefb6c10 SP	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
fefb6c10 SP	4	* Lead Tech Design <www.leadtechdesign.com>
fefb6c10 SP	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
fefb6c10 SP	7	*/
	8
	9	#include <common.h>
86592f60	10	#include <asm/io.h>
fefb6c10	11	#include <asm/arch/hardware.h>
983c1db0 SP	12	#include <asm/arch/at91_pit.h>
983c1db0 SP	13	#include <asm/arch/at91_pmc.h>
6ebff365	14	#include <asm/arch/clk.h>
6ebff365	15	#include <div64.h>
fefb6c10	16
5dca710a RM	17	#if !defined(CONFIG_AT91FAMILY)
	18	# error You need to define CONFIG_AT91FAMILY in your board config!
	19	#endif
	20
	21	DECLARE_GLOBAL_DATA_PTR;
	22
fefb6c10	23	/*
a8a78f2d	24	* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
fefb6c10	25	* setting the 20 bit counter period to its maximum (0xfffff).
5dca710a RM	26	* (See the relevant data sheets to understand that this really works)
	27	*
	28	* We do also mimic the typical powerpc way of incrementing
	29	* two 32 bit registers called tbl and tbu.
	30	*
	31	* Those registers increment at 1/16 the main clock rate.
fefb6c10	32	*/
fefb6c10	33
5dca710a	34	#define TIMER_LOAD_VAL 0xfffff
6ebff365	35
5dca710a RM	36	/*
	37	* Use the PITC in full 32 bit incrementing mode
	38	*/
61106a56	39	int timer_init(void)
fefb6c10	40	{
9f3fe90f RM	41	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
9f3fe90f RM	42	at91_pit_t pit = (at91_pit_t ) ATMEL_BASE_PIT;
5dca710a RM	43
5dca710a RM	44	/* Enable PITC Clock */
9f3fe90f	45	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
fefb6c10 SP	46
fefb6c10 SP	47	/* Enable PITC */
0cf0b931	48	writel(TIMER_LOAD_VAL \| AT91_PIT_MR_EN , &pit->mr);
fefb6c10	49
b339051c	50	gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
6ebff365	51
fefb6c10 SP	52	return 0;
	53	}
	54
fefb6c10	55	/*
5dca710a	56	* Return the number of timer ticks per second.
fefb6c10 SP	57	*/
	58	ulong get_tbclk(void)
	59	{
b339051c	60	return gd->arch.timer_rate_hz;
fefb6c10	61	}