[people/ms/u-boot.git] / arch / arm / mach-davinci / da850_lowlevel.c

/*
 * SoC-specific lowlevel code for DA850
 *
 * Copyright (C) 2011
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <nand.h>
#include <ns16550.h>
#include <post.h>
#include <asm/arch/da850_lowlevel.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/ti-common/davinci_nand.h>
#include <asm/arch/pll_defs.h>

void davinci_enable_uart0(void)
{
	lpsc_on(DAVINCI_LPSC_UART0);

	/* Bringup UART0 out of reset */
	REG(UART0_PWREMU_MGMT) = 0x00006001;
}

#if defined(CONFIG_SYS_DA850_PLL_INIT)
static void da850_waitloop(unsigned long loopcnt)
{
	unsigned long	i;

	for (i = 0; i < loopcnt; i++)
		asm("   NOP");
}

static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
{
	if (reg == davinci_pllc0_regs)
		/* Unlock PLL registers. */
		clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);

	/*
	 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
	 * through MMR
	 */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
	/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
	clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);

	/* Set PLLEN=0 => PLL BYPASS MODE */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);

	da850_waitloop(150);

	if (reg == davinci_pllc0_regs) {
		/*
		 * Select the Clock Mode bit 8 as External Clock or On Chip
		 * Oscilator
		 */
		dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
		setbits_le32(&reg->pllctl,
			(CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
	}

	/* Clear PLLRST bit to reset the PLL */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);

	/* Disable the PLL output */
	setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);

	/* PLL initialization sequence */
	/*
	 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
	 * power down bit
	 */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);

	/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);

#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
	/* program the prediv */
	if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
		writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
			&reg->prediv);
#endif

	/* Program the required multiplier value in PLLM */
	writel(pllmult, &reg->pllm);

	/* program the postdiv */
	if (reg == davinci_pllc0_regs)
		writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
			&reg->postdiv);
	else
		writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
			&reg->postdiv);

	/*
	 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
	 * no GO operation is currently in progress
	 */
	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
		;

	if (reg == davinci_pllc0_regs) {
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
	} else {
		writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
		writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
		writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
	}

	/*
	 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
	 * transition.
	 */
	setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);

	/*
	 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
	 * (completion of phase alignment).
	 */
	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
		;

	/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
	da850_waitloop(200);

	/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
	setbits_le32(&reg->pllctl, PLLCTL_PLLRST);

	/* Wait for PLL to lock. See PLL spec for PLL lock time */
	da850_waitloop(2400);

	/*
	 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
	 * mode
	 */
	setbits_le32(&reg->pllctl, PLLCTL_PLLEN);


	/*
	 * clear EMIFA and EMIFB clock source settings, let them
	 * run off SYSCLK
	 */
	if (reg == davinci_pllc0_regs)
		dv_maskbits(&davinci_syscfg_regs->cfgchip3,
			~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));

	return 0;
}
#endif /* CONFIG_SYS_DA850_PLL_INIT */

#if defined(CONFIG_SYS_DA850_DDR_INIT)
static int da850_ddr_setup(void)
{
	unsigned long	tmp;

	/* Enable the Clock to DDR2/mDDR */
	lpsc_on(DAVINCI_LPSC_DDR_EMIF);

	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
		/* Begin VTP Calibration */
		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);

		/* Polling READY bit to see when VTP calibration is done */
		tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
		while ((tmp & VTP_READY) != VTP_READY)
			tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);

		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
	}
	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);

	if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
		/* DDR2 */
		clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
			(1 << DDR_SLEW_DDR_PDENA_BIT) |
			(1 << DDR_SLEW_CMOSEN_BIT));
	} else {
		/* MOBILE DDR */
		setbits_le32(&davinci_syscfg1_regs->ddr_slew,
			(1 << DDR_SLEW_DDR_PDENA_BIT) |
			(1 << DDR_SLEW_CMOSEN_BIT));
	}

	/*
	 * SDRAM Configuration Register (SDCR):
	 * First set the BOOTUNLOCK bit to make configuration bits
	 * writeable.
	 */
	setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);

	/*
	 * Write the new value of these bits and clear BOOTUNLOCK.
	 * At the same time, set the TIMUNLOCK bit to allow changing
	 * the timing registers
	 */
	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
	tmp &= ~DV_DDR_BOOTUNLOCK;
	tmp |= DV_DDR_TIMUNLOCK;
	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);

	/* write memory configuration and timing */
	if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
		/* MOBILE DDR only*/
		writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
			&dv_ddr2_regs_ctrl->sdbcr2);
	}
	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);

	/* clear the TIMUNLOCK bit and write the value of the CL field */
	tmp &= ~DV_DDR_TIMUNLOCK;
	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);

	/*
	 * LPMODEN and MCLKSTOPEN must be set!
	 * Without this bits set, PSC don;t switch states !!
	 */
	writel(CONFIG_SYS_DA850_DDR2_SDRCR |
		(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
		(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
		&dv_ddr2_regs_ctrl->sdrcr);

	/* SyncReset the Clock to EMIF3A SDRAM */
	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
	/* Enable the Clock to EMIF3A SDRAM */
	lpsc_on(DAVINCI_LPSC_DDR_EMIF);

	/* disable self refresh */
	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
		DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);

	return 0;
}
#endif /* CONFIG_SYS_DA850_DDR_INIT */

__attribute__((weak))
void board_gpio_init(void)
{
	return;
}

int arch_cpu_init(void)
{
	/* Unlock kick registers */
	writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
	writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);

	dv_maskbits(&davinci_syscfg_regs->suspsrc,
		CONFIG_SYS_DA850_SYSCFG_SUSPSRC);

	/* configure pinmux settings */
	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
		return 1;

#if defined(CONFIG_SYS_DA850_PLL_INIT)
	/* PLL setup */
	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
#endif
	/* setup CSn config */
#if defined(CONFIG_SYS_DA850_CS2CFG)
	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
#endif
#if defined(CONFIG_SYS_DA850_CS3CFG)
	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
#endif

	da8xx_configure_lpsc_items(lpsc, lpsc_size);

	/* GPIO setup */
	board_gpio_init();


	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);

	/*
	 * Fix Power and Emulation Management Register
	 * see sprufw3a.pdf page 37 Table 24
	 */
	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
		DAVINCI_UART_PWREMU_MGMT_UTRST),
#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
#else
	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
#endif

#if defined(CONFIG_SYS_DA850_DDR_INIT)
	da850_ddr_setup();
#endif

	return 0;
}
Commit	Line	Data
310ae55e	1	/*
effea9d1	2	* SoC-specific lowlevel code for DA850
310ae55e HS	3	*
	4	* Copyright (C) 2011
	5	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
310ae55e HS	8	*/
	9	#include <common.h>
	10	#include <nand.h>
	11	#include <ns16550.h>
	12	#include <post.h>
effea9d1	13	#include <asm/arch/da850_lowlevel.h>
310ae55e	14	#include <asm/arch/hardware.h>
65204715	15	#include <asm/arch/davinci_misc.h>
310ae55e	16	#include <asm/arch/ddr2_defs.h>
3e01ed00	17	#include <asm/ti-common/davinci_nand.h>
f3c149d6	18	#include <asm/arch/pll_defs.h>
310ae55e	19
81ac7e51 EB	20	void davinci_enable_uart0(void)
	21	{
	22	lpsc_on(DAVINCI_LPSC_UART0);
	23
	24	/* Bringup UART0 out of reset */
	25	REG(UART0_PWREMU_MGMT) = 0x00006001;
	26	}
	27
6b873dca	28	#if defined(CONFIG_SYS_DA850_PLL_INIT)
893b92f8	29	static void da850_waitloop(unsigned long loopcnt)
310ae55e HS	30	{
	31	unsigned long i;
	32
	33	for (i = 0; i < loopcnt; i++)
	34	asm(" NOP");
	35	}
	36
893b92f8	37	static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
310ae55e HS	38	{
	39	if (reg == davinci_pllc0_regs)
	40	/* Unlock PLL registers. */
f3c149d6	41	clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
310ae55e HS	42
	43	/*
	44	* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
	45	* through MMR
	46	*/
f3c149d6	47	clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
310ae55e	48	/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
f3c149d6	49	clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
310ae55e HS	50
310ae55e HS	51	/* Set PLLEN=0 => PLL BYPASS MODE */
f3c149d6	52	clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
310ae55e	53
effea9d1	54	da850_waitloop(150);
310ae55e HS	55
	56	if (reg == davinci_pllc0_regs) {
	57	/*
	58	* Select the Clock Mode bit 8 as External Clock or On Chip
	59	* Oscilator
	60	*/
f3c149d6 HS	61	dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
	62	setbits_le32(&reg->pllctl,
	63	(CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
310ae55e HS	64	}
	65
	66	/* Clear PLLRST bit to reset the PLL */
f3c149d6	67	clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
310ae55e HS	68
310ae55e HS	69	/* Disable the PLL output */
f3c149d6	70	setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
310ae55e HS	71
	72	/* PLL initialization sequence */
	73	/*
	74	* Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
	75	* power down bit
	76	*/
f3c149d6	77	clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
310ae55e HS	78
310ae55e HS	79	/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
f3c149d6	80	clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
310ae55e	81
d652a344 BG	82	#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
	83	/* program the prediv */
	84	if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
	85	writel((PLL_DIVEN \| CONFIG_SYS_DA850_PLL0_PREDIV),
	86	&reg->prediv);
	87	#endif
	88
310ae55e HS	89	/* Program the required multiplier value in PLLM */
	90	writel(pllmult, &reg->pllm);
	91
	92	/* program the postdiv */
	93	if (reg == davinci_pllc0_regs)
f3c149d6	94	writel((PLL_POSTDEN \| CONFIG_SYS_DA850_PLL0_POSTDIV),
310ae55e HS	95	&reg->postdiv);
310ae55e HS	96	else
f3c149d6	97	writel((PLL_POSTDEN \| CONFIG_SYS_DA850_PLL1_POSTDIV),
310ae55e HS	98	&reg->postdiv);
	99
	100	/*
	101	* Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
	102	* no GO operation is currently in progress
	103	*/
f3c149d6	104	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
310ae55e HS	105	;
	106
	107	if (reg == davinci_pllc0_regs) {
effea9d1 CR	108	writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
	109	writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
	110	writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
	111	writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
	112	writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
	113	writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
	114	writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
310ae55e	115	} else {
effea9d1 CR	116	writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
	117	writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
	118	writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
310ae55e HS	119	}
	120
	121	/*
	122	* Set the GOSET bit in PLLCMD to 1 to initiate a new divider
	123	* transition.
	124	*/
f3c149d6	125	setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
310ae55e HS	126
	127	/*
	128	* Wait for the GOSTAT bit in PLLSTAT to clear to 0
	129	* (completion of phase alignment).
	130	*/
f3c149d6	131	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
310ae55e HS	132	;
	133
	134	/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
effea9d1	135	da850_waitloop(200);
310ae55e HS	136
310ae55e HS	137	/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
f3c149d6	138	setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
310ae55e HS	139
310ae55e HS	140	/* Wait for PLL to lock. See PLL spec for PLL lock time */
effea9d1	141	da850_waitloop(2400);
310ae55e HS	142
	143	/*
	144	* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
	145	* mode
	146	*/
f3c149d6	147	setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
310ae55e HS	148
	149
	150	/*
	151	* clear EMIFA and EMIFB clock source settings, let them
	152	* run off SYSCLK
	153	*/
	154	if (reg == davinci_pllc0_regs)
f3c149d6 HS	155	dv_maskbits(&davinci_syscfg_regs->cfgchip3,
f3c149d6 HS	156	~(PLL_SCSCFG3_DIV45PENA \| PLL_SCSCFG3_EMA_CLKSRC));
310ae55e HS	157
	158	return 0;
	159	}
6b873dca	160	#endif /* CONFIG_SYS_DA850_PLL_INIT */
310ae55e	161
6b873dca	162	#if defined(CONFIG_SYS_DA850_DDR_INIT)
893b92f8	163	static int da850_ddr_setup(void)
310ae55e HS	164	{
	165	unsigned long tmp;
	166
	167	/* Enable the Clock to DDR2/mDDR */
95c248f4	168	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
310ae55e HS	169
	170	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	171	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
	172	/* Begin VTP Calibration */
	173	clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
	174	clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
	175	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
	176	clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
	177	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
	178
	179	/* Polling READY bit to see when VTP calibration is done */
	180	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	181	while ((tmp & VTP_READY) != VTP_READY)
	182	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	183
	184	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
	185	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
310ae55e	186	}
89473d23	187	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
effea9d1	188	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
89473d23 MK	189
	190	if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
	191	/* DDR2 */
	192	clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
	193	(1 << DDR_SLEW_DDR_PDENA_BIT) \|
	194	(1 << DDR_SLEW_CMOSEN_BIT));
	195	} else {
	196	/* MOBILE DDR */
	197	setbits_le32(&davinci_syscfg1_regs->ddr_slew,
	198	(1 << DDR_SLEW_DDR_PDENA_BIT) \|
	199	(1 << DDR_SLEW_CMOSEN_BIT));
	200	}
310ae55e	201
085d4574 CR	202	/*
	203	* SDRAM Configuration Register (SDCR):
	204	* First set the BOOTUNLOCK bit to make configuration bits
	205	* writeable.
	206	*/
310ae55e HS	207	setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
310ae55e HS	208
085d4574 CR	209	/*
	210	* Write the new value of these bits and clear BOOTUNLOCK.
	211	* At the same time, set the TIMUNLOCK bit to allow changing
	212	* the timing registers
	213	*/
	214	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
f3c149d6 HS	215	tmp &= ~DV_DDR_BOOTUNLOCK;
f3c149d6 HS	216	tmp \|= DV_DDR_TIMUNLOCK;
085d4574	217	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
310ae55e	218
085d4574	219	/* write memory configuration and timing */
89473d23 MK	220	if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
	221	/* MOBILE DDR only*/
	222	writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
	223	&dv_ddr2_regs_ctrl->sdbcr2);
	224	}
effea9d1 CR	225	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
effea9d1 CR	226	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
310ae55e	227
085d4574	228	/* clear the TIMUNLOCK bit and write the value of the CL field */
f3c149d6	229	tmp &= ~DV_DDR_TIMUNLOCK;
085d4574	230	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
310ae55e HS	231
	232	/*
	233	* LPMODEN and MCLKSTOPEN must be set!
	234	* Without this bits set, PSC don;t switch states !!
	235	*/
effea9d1	236	writel(CONFIG_SYS_DA850_DDR2_SDRCR \|
310ae55e HS	237	(1 << DV_DDR_SRCR_LPMODEN_SHIFT) \|
	238	(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
	239	&dv_ddr2_regs_ctrl->sdrcr);
	240
	241	/* SyncReset the Clock to EMIF3A SDRAM */
95c248f4	242	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
310ae55e	243	/* Enable the Clock to EMIF3A SDRAM */
95c248f4	244	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
310ae55e HS	245
310ae55e HS	246	/* disable self refresh */
f3c149d6	247	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
89473d23	248	DV_DDR_SDRCR_LPMODEN \| DV_DDR_SDRCR_MCLKSTOPEN);
f3c149d6	249	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
310ae55e HS	250
	251	return 0;
	252	}
6b873dca	253	#endif /* CONFIG_SYS_DA850_DDR_INIT */
310ae55e	254
310ae55e HS	255	__attribute__((weak))
	256	void board_gpio_init(void)
	257	{
	258	return;
	259	}
	260
310ae55e	261	int arch_cpu_init(void)
310ae55e	262	{
310ae55e	263	/* Unlock kick registers */
f3c149d6 HS	264	writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
f3c149d6 HS	265	writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
310ae55e HS	266
310ae55e HS	267	dv_maskbits(&davinci_syscfg_regs->suspsrc,
f3c149d6	268	CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
310ae55e	269
65204715 CR	270	/* configure pinmux settings */
	271	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
	272	return 1;
310ae55e	273
6b873dca	274	#if defined(CONFIG_SYS_DA850_PLL_INIT)
310ae55e	275	/* PLL setup */
effea9d1 CR	276	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
effea9d1 CR	277	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
6b873dca	278	#endif
310ae55e	279	/* setup CSn config */
f3c149d6	280	#if defined(CONFIG_SYS_DA850_CS2CFG)
effea9d1	281	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
f3c149d6 HS	282	#endif
f3c149d6 HS	283	#if defined(CONFIG_SYS_DA850_CS3CFG)
effea9d1	284	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
f3c149d6	285	#endif
310ae55e	286
6b873dca SG	287	da8xx_configure_lpsc_items(lpsc, lpsc_size);
	288
	289	/* GPIO setup */
	290	board_gpio_init();
	291
	292
310ae55e HS	293	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
	294	CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
	295
	296	/*
	297	* Fix Power and Emulation Management Register
	298	* see sprufw3a.pdf page 37 Table 24
	299	*/
f3c149d6 HS	300	writel((DAVINCI_UART_PWREMU_MGMT_FREE \| DAVINCI_UART_PWREMU_MGMT_URRST \|
f3c149d6 HS	301	DAVINCI_UART_PWREMU_MGMT_UTRST),
9c8deaee HS	302	#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
	303	&davinci_uart0_ctrl_regs->pwremu_mgmt);
	304	#else
f3c149d6	305	&davinci_uart2_ctrl_regs->pwremu_mgmt);
9c8deaee	306	#endif
310ae55e	307
6b873dca	308	#if defined(CONFIG_SYS_DA850_DDR_INIT)
f3c149d6	309	da850_ddr_setup();
6b873dca SG	310	#endif
6b873dca SG	311
310ae55e	312	return 0;
310ae55e	313	}