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840f8923 SP |
1 | /* |
2 | * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
840f8923 SP |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <net.h> | |
11 | #include <miiphy.h> | |
12 | #include <asm/arch/emac_defs.h> | |
601fbec7 | 13 | #include "../../../drivers/net/davinci_emac.h" |
840f8923 SP |
14 | |
15 | #ifdef CONFIG_DRIVER_TI_EMAC | |
16 | ||
17 | #ifdef CONFIG_CMD_NET | |
18 | ||
19 | /* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */ | |
20 | ||
21 | #define MII_PHY_CONFIG_REG 22 | |
22 | ||
23 | /* PHY Config bits */ | |
24 | #define PHY_SYS_CLK_EN (1 << 4) | |
25 | ||
26 | int et1011c_get_link_speed(int phy_addr) | |
27 | { | |
28 | u_int16_t data; | |
29 | ||
30 | if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) { | |
fb1d6332 | 31 | davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data); |
840f8923 | 32 | /* Enable 125MHz clock sourced from PHY */ |
fb1d6332 | 33 | davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG, |
840f8923 SP |
34 | data | PHY_SYS_CLK_EN); |
35 | return (1); | |
36 | } | |
37 | return (0); | |
38 | } | |
39 | ||
40 | #endif /* CONFIG_CMD_NET */ | |
41 | ||
42 | #endif /* CONFIG_DRIVER_ETHER */ |