[people/ms/u-boot.git] / arch / arm / mach-davinci / psc.c

/*
 * Power and Sleep Controller (PSC) functions.
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
 * Copyright (C) 2004 Texas Instruments.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>

/*
 * The PSC manages three inputs to a "module" which may be a peripheral or
 * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
 * its power domain.  For our purposes, we only care whether clock and power
 * are active, and the module is out of reset.
 *
 * DaVinci chips may include two separate power domains: "Always On" and "DSP".
 * Chips without a DSP generally have only one domain.
 *
 * The "Always On" power domain is always on when the chip is on, and is
 * powered by the VDD pins (on DM644X). The majority of DaVinci modules
 * lie within the "Always On" power domain.
 *
 * A separate domain called the "DSP" domain houses the C64x+ and other video
 * hardware such as VICP. In some chips, the "DSP" domain is not always on.
 * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
 */

/* Works on Always On power domain only (no PD argument) */
static void lpsc_transition(unsigned int id, unsigned int state)
{
	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
#ifdef CONFIG_SOC_DA8XX
	struct davinci_psc_regs *psc_regs;
#endif

#ifndef CONFIG_SOC_DA8XX
	if (id >= DAVINCI_LPSC_GEM)
		return;			/* Don't work on DSP Power Domain */

	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
	ptstat = REG_P(PSC_PTSTAT);
	ptcmd = REG_P(PSC_PTCMD);
#else
	if (id < DAVINCI_LPSC_PSC1_BASE) {
		if (id >= PSC_PSC0_MODULE_ID_CNT)
			return;
		psc_regs = davinci_psc0_regs;
		mdstat = &psc_regs->psc0.mdstat[id];
		mdctl = &psc_regs->psc0.mdctl[id];
	} else {
		id -= DAVINCI_LPSC_PSC1_BASE;
		if (id >= PSC_PSC1_MODULE_ID_CNT)
			return;
		psc_regs = davinci_psc1_regs;
		mdstat = &psc_regs->psc1.mdstat[id];
		mdctl = &psc_regs->psc1.mdctl[id];
	}
	ptstat = &psc_regs->ptstat;
	ptcmd = &psc_regs->ptcmd;
#endif

	while (readl(ptstat) & 0x01)
		continue;

	if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
		return; /* Already in that state */

	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);

	switch (id) {
#ifdef CONFIG_SOC_DM644X
	/* Special treatment for some modules as for sprue14 p.7.4.2 */
	case DAVINCI_LPSC_VPSSSLV:
	case DAVINCI_LPSC_EMAC:
	case DAVINCI_LPSC_EMAC_WRAPPER:
	case DAVINCI_LPSC_MDIO:
	case DAVINCI_LPSC_USB:
	case DAVINCI_LPSC_ATA:
	case DAVINCI_LPSC_VLYNQ:
	case DAVINCI_LPSC_UHPI:
	case DAVINCI_LPSC_DDR_EMIF:
	case DAVINCI_LPSC_AEMIF:
	case DAVINCI_LPSC_MMC_SD:
	case DAVINCI_LPSC_MEMSTICK:
	case DAVINCI_LPSC_McBSP:
	case DAVINCI_LPSC_GPIO:
		writel(readl(mdctl) | 0x200, mdctl);
		break;
#endif
	}

	writel(0x01, ptcmd);

	while (readl(ptstat) & 0x01)
		continue;
	while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
		continue;
}

void lpsc_on(unsigned int id)
{
	lpsc_transition(id, 0x03);
}

void lpsc_syncreset(unsigned int id)
{
	lpsc_transition(id, 0x01);
}

void lpsc_disable(unsigned int id)
{
	lpsc_transition(id, 0x0);
}

/* Not all DaVinci chips have a DSP power domain. */
#ifdef CONFIG_SOC_DM644X

/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
#if !defined(CONFIG_SYS_USE_DSPLINK)
void dsp_on(void)
{
	int i;

	if (REG(PSC_PDSTAT1) & 0x1f)
		return;			/* Already on */

	REG(PSC_GBLCTL) |= 0x01;
	REG(PSC_PDCTL1) |= 0x01;
	REG(PSC_PDCTL1) &= ~0x100;
	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
	REG(PSC_PTCMD) = 0x02;

	for (i = 0; i < 100; i++) {
		if (REG(PSC_EPCPR) & 0x02)
			break;
	}

	REG(PSC_CHP_SHRTSW) = 0x01;
	REG(PSC_PDCTL1) |= 0x100;
	REG(PSC_EPCCR) = 0x02;

	for (i = 0; i < 100; i++) {
		if (!(REG(PSC_PTSTAT) & 0x02))
			break;
	}

	REG(PSC_GBLCTL) &= ~0x1f;
}
#endif /* CONFIG_SYS_USE_DSPLINK */

#endif /* have a DSP */
Commit	Line	Data
264bbdd1 HV	1	/*
	2	* Power and Sleep Controller (PSC) functions.
	3	*
	4	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	5	* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
	6	* Copyright (C) 2004 Texas Instruments.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
264bbdd1 HV	9	*/
	10
	11	#include <common.h>
	12	#include <asm/arch/hardware.h>
91172baf	13	#include <asm/io.h>
264bbdd1 HV	14
264bbdd1 HV	15	/*
f7904368 DB	16	* The PSC manages three inputs to a "module" which may be a peripheral or
	17	* CPU. Those inputs are the module's: clock; reset signal; and sometimes
	18	* its power domain. For our purposes, we only care whether clock and power
	19	* are active, and the module is out of reset.
	20	*
	21	* DaVinci chips may include two separate power domains: "Always On" and "DSP".
	22	* Chips without a DSP generally have only one domain.
	23	*
	24	* The "Always On" power domain is always on when the chip is on, and is
	25	* powered by the VDD pins (on DM644X). The majority of DaVinci modules
	26	* lie within the "Always On" power domain.
	27	*
	28	* A separate domain called the "DSP" domain houses the C64x+ and other video
	29	* hardware such as VICP. In some chips, the "DSP" domain is not always on.
	30	* The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
264bbdd1 HV	31	*/
	32
	33	/* Works on Always On power domain only (no PD argument) */
fab19c14	34	static void lpsc_transition(unsigned int id, unsigned int state)
264bbdd1	35	{
91172baf SN	36	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
	37	#ifdef CONFIG_SOC_DA8XX
	38	struct davinci_psc_regs *psc_regs;
	39	#endif
264bbdd1	40
91172baf	41	#ifndef CONFIG_SOC_DA8XX
264bbdd1 HV	42	if (id >= DAVINCI_LPSC_GEM)
	43	return; /* Don't work on DSP Power Domain */
	44
	45	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
	46	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
91172baf SN	47	ptstat = REG_P(PSC_PTSTAT);
	48	ptcmd = REG_P(PSC_PTCMD);
	49	#else
	50	if (id < DAVINCI_LPSC_PSC1_BASE) {
	51	if (id >= PSC_PSC0_MODULE_ID_CNT)
	52	return;
	53	psc_regs = davinci_psc0_regs;
	54	mdstat = &psc_regs->psc0.mdstat[id];
	55	mdctl = &psc_regs->psc0.mdctl[id];
	56	} else {
	57	id -= DAVINCI_LPSC_PSC1_BASE;
	58	if (id >= PSC_PSC1_MODULE_ID_CNT)
	59	return;
	60	psc_regs = davinci_psc1_regs;
	61	mdstat = &psc_regs->psc1.mdstat[id];
	62	mdctl = &psc_regs->psc1.mdctl[id];
	63	}
	64	ptstat = &psc_regs->ptstat;
	65	ptcmd = &psc_regs->ptcmd;
	66	#endif
264bbdd1	67
91172baf	68	while (readl(ptstat) & 0x01)
f7904368	69	continue;
264bbdd1	70
fab19c14 CR	71	if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
fab19c14 CR	72	return; /* Already in that state */
264bbdd1	73
fab19c14	74	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) \| state, mdctl);
264bbdd1	75
264bbdd1	76	switch (id) {
f7904368 DB	77	#ifdef CONFIG_SOC_DM644X
f7904368 DB	78	/* Special treatment for some modules as for sprue14 p.7.4.2 */
264bbdd1 HV	79	case DAVINCI_LPSC_VPSSSLV:
	80	case DAVINCI_LPSC_EMAC:
	81	case DAVINCI_LPSC_EMAC_WRAPPER:
	82	case DAVINCI_LPSC_MDIO:
	83	case DAVINCI_LPSC_USB:
	84	case DAVINCI_LPSC_ATA:
	85	case DAVINCI_LPSC_VLYNQ:
	86	case DAVINCI_LPSC_UHPI:
	87	case DAVINCI_LPSC_DDR_EMIF:
	88	case DAVINCI_LPSC_AEMIF:
	89	case DAVINCI_LPSC_MMC_SD:
	90	case DAVINCI_LPSC_MEMSTICK:
	91	case DAVINCI_LPSC_McBSP:
	92	case DAVINCI_LPSC_GPIO:
91172baf	93	writel(readl(mdctl) \| 0x200, mdctl);
264bbdd1	94	break;
f7904368	95	#endif
264bbdd1 HV	96	}
264bbdd1 HV	97
91172baf	98	writel(0x01, ptcmd);
264bbdd1	99
91172baf	100	while (readl(ptstat) & 0x01)
f7904368	101	continue;
fab19c14	102	while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
f7904368	103	continue;
264bbdd1 HV	104	}
264bbdd1 HV	105
fab19c14 CR	106	void lpsc_on(unsigned int id)
	107	{
	108	lpsc_transition(id, 0x03);
	109	}
	110
	111	void lpsc_syncreset(unsigned int id)
	112	{
	113	lpsc_transition(id, 0x01);
	114	}
	115
25f8bf6e SG	116	void lpsc_disable(unsigned int id)
	117	{
	118	lpsc_transition(id, 0x0);
	119	}
	120
f7904368 DB	121	/* Not all DaVinci chips have a DSP power domain. */
	122	#ifdef CONFIG_SOC_DM644X
	123
264bbdd1	124	/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
6d0f6bcf	125	#if !defined(CONFIG_SYS_USE_DSPLINK)
264bbdd1 HV	126	void dsp_on(void)
	127	{
	128	int i;
	129
	130	if (REG(PSC_PDSTAT1) & 0x1f)
	131	return; /* Already on */
	132
	133	REG(PSC_GBLCTL) \|= 0x01;
	134	REG(PSC_PDCTL1) \|= 0x01;
	135	REG(PSC_PDCTL1) &= ~0x100;
	136	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) \|= 0x03;
	137	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
	138	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) \|= 0x03;
	139	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
	140	REG(PSC_PTCMD) = 0x02;
	141
	142	for (i = 0; i < 100; i++) {
	143	if (REG(PSC_EPCPR) & 0x02)
	144	break;
	145	}
	146
	147	REG(PSC_CHP_SHRTSW) = 0x01;
	148	REG(PSC_PDCTL1) \|= 0x100;
	149	REG(PSC_EPCCR) = 0x02;
	150
	151	for (i = 0; i < 100; i++) {
	152	if (!(REG(PSC_PTSTAT) & 0x02))
	153	break;
	154	}
	155
	156	REG(PSC_GBLCTL) &= ~0x1f;
	157	}
6d0f6bcf	158	#endif /* CONFIG_SYS_USE_DSPLINK */
0cd18fa9	159
f7904368	160	#endif /* have a DSP */