[people/ms/u-boot.git] / arch / arm / mach-imx / hab.c

/*
 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:    GPL-2.0+
 */

#include <common.h>
#include <config.h>
#include <fuse.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/hab.h>

/* -------- start of HAB API updates ------------*/

#define hab_rvt_report_event_p					\
(								\
	(is_mx6dqp()) ?						\
	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)	\
)

#define hab_rvt_report_status_p					\
(								\
	(is_mx6dqp()) ?						\
	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)	\
)

#define hab_rvt_authenticate_image_p				\
(								\
	(is_mx6dqp()) ?						\
	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)	\
)

#define hab_rvt_entry_p						\
(								\
	(is_mx6dqp()) ?						\
	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
	((hab_rvt_entry_t *)HAB_RVT_ENTRY)			\
)

#define hab_rvt_exit_p						\
(								\
	(is_mx6dqp()) ?						\
	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
	((hab_rvt_exit_t *)HAB_RVT_EXIT)			\
)

#define IVT_SIZE		0x20
#define ALIGN_SIZE		0x1000
#define CSF_PAD_SIZE		0x2000
#define MX6DQ_PU_IROM_MMU_EN_VAR	0x009024a8
#define MX6DLS_PU_IROM_MMU_EN_VAR	0x00901dd0
#define MX6SL_PU_IROM_MMU_EN_VAR	0x00900a18
#define IS_HAB_ENABLED_BIT \
	(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 :	\
	 (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))

/*
 * +------------+  0x0 (DDR_UIMAGE_START) -
 * |   Header   |                          |
 * +------------+  0x40                    |
 * |            |                          |
 * |            |                          |
 * |            |                          |
 * |            |                          |
 * | Image Data |                          |
 * .            |                          |
 * .            |                           > Stuff to be authenticated ----+
 * .            |                          |                                |
 * |            |                          |                                |
 * |            |                          |                                |
 * +------------+                          |                                |
 * |            |                          |                                |
 * | Fill Data  |                          |                                |
 * |            |                          |                                |
 * +------------+ Align to ALIGN_SIZE      |                                |
 * |    IVT     |                          |                                |
 * +------------+ + IVT_SIZE              -                                 |
 * |            |                                                           |
 * |  CSF DATA  | <---------------------------------------------------------+
 * |            |
 * +------------+
 * |            |
 * | Fill Data  |
 * |            |
 * +------------+ + CSF_PAD_SIZE
 */

static bool is_hab_enabled(void);

#if !defined(CONFIG_SPL_BUILD)

#define MAX_RECORD_BYTES     (8*1024) /* 4 kbytes */

struct record {
	uint8_t  tag;						/* Tag */
	uint8_t  len[2];					/* Length */
	uint8_t  par;						/* Version */
	uint8_t  contents[MAX_RECORD_BYTES];/* Record Data */
	bool	 any_rec_flag;
};

char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
				   "RSN = HAB_ENG_FAIL (0x30)\n",
				   "RSN = HAB_INV_ADDRESS (0x22)\n",
				   "RSN = HAB_INV_ASSERTION (0x0C)\n",
				   "RSN = HAB_INV_CALL (0x28)\n",
				   "RSN = HAB_INV_CERTIFICATE (0x21)\n",
				   "RSN = HAB_INV_COMMAND (0x06)\n",
				   "RSN = HAB_INV_CSF (0x11)\n",
				   "RSN = HAB_INV_DCD (0x27)\n",
				   "RSN = HAB_INV_INDEX (0x0F)\n",
				   "RSN = HAB_INV_IVT (0x05)\n",
				   "RSN = HAB_INV_KEY (0x1D)\n",
				   "RSN = HAB_INV_RETURN (0x1E)\n",
				   "RSN = HAB_INV_SIGNATURE (0x18)\n",
				   "RSN = HAB_INV_SIZE (0x17)\n",
				   "RSN = HAB_MEM_FAIL (0x2E)\n",
				   "RSN = HAB_OVR_COUNT (0x2B)\n",
				   "RSN = HAB_OVR_STORAGE (0x2D)\n",
				   "RSN = HAB_UNS_ALGORITHM (0x12)\n",
				   "RSN = HAB_UNS_COMMAND (0x03)\n",
				   "RSN = HAB_UNS_ENGINE (0x0A)\n",
				   "RSN = HAB_UNS_ITEM (0x24)\n",
				   "RSN = HAB_UNS_KEY (0x1B)\n",
				   "RSN = HAB_UNS_PROTOCOL (0x14)\n",
				   "RSN = HAB_UNS_STATE (0x09)\n",
				   "RSN = INVALID\n",
				   NULL};

char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
				   "STS = HAB_FAILURE (0x33)\n",
				   "STS = HAB_WARNING (0x69)\n",
				   "STS = INVALID\n",
				   NULL};

char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
				   "ENG = HAB_ENG_SCC (0x03)\n",
				   "ENG = HAB_ENG_RTIC (0x05)\n",
				   "ENG = HAB_ENG_SAHARA (0x06)\n",
				   "ENG = HAB_ENG_CSU (0x0A)\n",
				   "ENG = HAB_ENG_SRTC (0x0C)\n",
				   "ENG = HAB_ENG_DCP (0x1B)\n",
				   "ENG = HAB_ENG_CAAM (0x1D)\n",
				   "ENG = HAB_ENG_SNVS (0x1E)\n",
				   "ENG = HAB_ENG_OCOTP (0x21)\n",
				   "ENG = HAB_ENG_DTCP (0x22)\n",
				   "ENG = HAB_ENG_ROM (0x36)\n",
				   "ENG = HAB_ENG_HDCP (0x24)\n",
				   "ENG = HAB_ENG_RTL (0x77)\n",
				   "ENG = HAB_ENG_SW (0xFF)\n",
				   "ENG = INVALID\n",
				   NULL};

char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
				   "CTX = HAB_CTX_FAB (0xFF)\n",
				   "CTX = HAB_CTX_ENTRY (0xE1)\n",
				   "CTX = HAB_CTX_TARGET (0x33)\n",
				   "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
				   "CTX = HAB_CTX_DCD (0xDD)\n",
				   "CTX = HAB_CTX_CSF (0xCF)\n",
				   "CTX = HAB_CTX_COMMAND (0xC0)\n",
				   "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
				   "CTX = HAB_CTX_ASSERT (0xA0)\n",
				   "CTX = HAB_CTX_EXIT (0xEE)\n",
				   "CTX = INVALID\n",
				   NULL};

uint8_t hab_statuses[5] = {
	HAB_STS_ANY,
	HAB_FAILURE,
	HAB_WARNING,
	HAB_SUCCESS,
	-1
};

uint8_t hab_reasons[26] = {
	HAB_RSN_ANY,
	HAB_ENG_FAIL,
	HAB_INV_ADDRESS,
	HAB_INV_ASSERTION,
	HAB_INV_CALL,
	HAB_INV_CERTIFICATE,
	HAB_INV_COMMAND,
	HAB_INV_CSF,
	HAB_INV_DCD,
	HAB_INV_INDEX,
	HAB_INV_IVT,
	HAB_INV_KEY,
	HAB_INV_RETURN,
	HAB_INV_SIGNATURE,
	HAB_INV_SIZE,
	HAB_MEM_FAIL,
	HAB_OVR_COUNT,
	HAB_OVR_STORAGE,
	HAB_UNS_ALGORITHM,
	HAB_UNS_COMMAND,
	HAB_UNS_ENGINE,
	HAB_UNS_ITEM,
	HAB_UNS_KEY,
	HAB_UNS_PROTOCOL,
	HAB_UNS_STATE,
	-1
};

uint8_t hab_contexts[12] = {
	HAB_CTX_ANY,
	HAB_CTX_FAB,
	HAB_CTX_ENTRY,
	HAB_CTX_TARGET,
	HAB_CTX_AUTHENTICATE,
	HAB_CTX_DCD,
	HAB_CTX_CSF,
	HAB_CTX_COMMAND,
	HAB_CTX_AUT_DAT,
	HAB_CTX_ASSERT,
	HAB_CTX_EXIT,
	-1
};

uint8_t hab_engines[16] = {
	HAB_ENG_ANY,
	HAB_ENG_SCC,
	HAB_ENG_RTIC,
	HAB_ENG_SAHARA,
	HAB_ENG_CSU,
	HAB_ENG_SRTC,
	HAB_ENG_DCP,
	HAB_ENG_CAAM,
	HAB_ENG_SNVS,
	HAB_ENG_OCOTP,
	HAB_ENG_DTCP,
	HAB_ENG_ROM,
	HAB_ENG_HDCP,
	HAB_ENG_RTL,
	HAB_ENG_SW,
	-1
};

static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
{
	uint8_t idx = 0;
	uint8_t element = list[idx];
	while (element != -1) {
		if (element == tgt)
			return idx;
		element = list[++idx];
	}
	return -1;
}

void process_event_record(uint8_t *event_data, size_t bytes)
{
	struct record *rec = (struct record *)event_data;

	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
}

void display_event(uint8_t *event_data, size_t bytes)
{
	uint32_t i;

	if (!(event_data && bytes > 0))
		return;

	for (i = 0; i < bytes; i++) {
		if (i == 0)
			printf("\t0x%02x", event_data[i]);
		else if ((i % 8) == 0)
			printf("\n\t0x%02x", event_data[i]);
		else
			printf(" 0x%02x", event_data[i]);
	}

	process_event_record(event_data, bytes);
}

int get_hab_status(void)
{
	uint32_t index = 0; /* Loop index */
	uint8_t event_data[128]; /* Event data buffer */
	size_t bytes = sizeof(event_data); /* Event size in bytes */
	enum hab_config config = 0;
	enum hab_state state = 0;
	hab_rvt_report_event_t *hab_rvt_report_event;
	hab_rvt_report_status_t *hab_rvt_report_status;

	hab_rvt_report_event = hab_rvt_report_event_p;
	hab_rvt_report_status = hab_rvt_report_status_p;

	if (is_hab_enabled())
		puts("\nSecure boot enabled\n");
	else
		puts("\nSecure boot disabled\n");

	/* Check HAB status */
	if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
		printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
		       config, state);

		/* Display HAB Error events */
		while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
					&bytes) == HAB_SUCCESS) {
			puts("\n");
			printf("--------- HAB Event %d -----------------\n",
			       index + 1);
			puts("event data:\n");
			display_event(event_data, bytes);
			puts("\n");
			bytes = sizeof(event_data);
			index++;
		}
	}
	/* Display message if no HAB events are found */
	else {
		printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
		       config, state);
		puts("No HAB Events Found!\n\n");
	}
	return 0;
}

int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	if ((argc != 1)) {
		cmd_usage(cmdtp);
		return 1;
	}

	get_hab_status();

	return 0;
}

static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
				char * const argv[])
{
	ulong	addr, ivt_offset;
	int	rcode = 0;

	if (argc < 3)
		return CMD_RET_USAGE;

	addr = simple_strtoul(argv[1], NULL, 16);
	ivt_offset = simple_strtoul(argv[2], NULL, 16);

	rcode = authenticate_image(addr, ivt_offset);
	if (rcode == 0)
		rcode = CMD_RET_SUCCESS;
	else
		rcode = CMD_RET_FAILURE;
	return rcode;
}

U_BOOT_CMD(
		hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
		"display HAB status",
		""
	  );

U_BOOT_CMD(
		hab_auth_img, 3, 0, do_authenticate_image,
		"authenticate image via HAB",
		"addr ivt_offset\n"
		"addr - image hex address\n"
		"ivt_offset - hex offset of IVT in the image"
	  );


#endif /* !defined(CONFIG_SPL_BUILD) */

static bool is_hab_enabled(void)
{
	struct imx_sec_config_fuse_t *fuse =
		(struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
	uint32_t reg;
	int ret;

	ret = fuse_read(fuse->bank, fuse->word, &reg);
	if (ret) {
		puts("\nSecure boot fuse read error\n");
		return ret;
	}

	return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
}

int authenticate_image(uint32_t ddr_start, uint32_t image_size)
{
	uint32_t load_addr = 0;
	size_t bytes;
	ptrdiff_t ivt_offset = 0;
	int result = 1;
	ulong start;
	hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
	hab_rvt_entry_t *hab_rvt_entry;
	hab_rvt_exit_t *hab_rvt_exit;

	hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
	hab_rvt_entry = hab_rvt_entry_p;
	hab_rvt_exit = hab_rvt_exit_p;

	if (is_hab_enabled()) {
		printf("\nAuthenticate image from DDR location 0x%x...\n",
		       ddr_start);

		hab_caam_clock_enable(1);

		if (hab_rvt_entry() == HAB_SUCCESS) {
			/* If not already aligned, Align to ALIGN_SIZE */
			ivt_offset = (image_size + ALIGN_SIZE - 1) &
					~(ALIGN_SIZE - 1);

			start = ddr_start;
			bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
#ifdef DEBUG
			printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
			       ivt_offset, ddr_start + ivt_offset);
			puts("Dumping IVT\n");
			print_buffer(ddr_start + ivt_offset,
				     (void *)(ddr_start + ivt_offset),
				     4, 0x8, 0);

			puts("Dumping CSF Header\n");
			print_buffer(ddr_start + ivt_offset+IVT_SIZE,
				     (void *)(ddr_start + ivt_offset+IVT_SIZE),
				     4, 0x10, 0);

#if  !defined(CONFIG_SPL_BUILD)
			get_hab_status();
#endif

			puts("\nCalling authenticate_image in ROM\n");
			printf("\tivt_offset = 0x%x\n", ivt_offset);
			printf("\tstart = 0x%08lx\n", start);
			printf("\tbytes = 0x%x\n", bytes);
#endif
			/*
			 * If the MMU is enabled, we have to notify the ROM
			 * code, or it won't flush the caches when needed.
			 * This is done, by setting the "pu_irom_mmu_enabled"
			 * word to 1. You can find its address by looking in
			 * the ROM map. This is critical for
			 * authenticate_image(). If MMU is enabled, without
			 * setting this bit, authentication will fail and may
			 * crash.
			 */
			/* Check MMU enabled */
			if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
				if (is_mx6dq()) {
					/*
					 * This won't work on Rev 1.0.0 of
					 * i.MX6Q/D, since their ROM doesn't
					 * do cache flushes. don't think any
					 * exist, so we ignore them.
					 */
					if (!is_mx6dqp())
						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
				} else if (is_mx6sdl()) {
					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
				} else if (is_mx6sl()) {
					writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
				}
			}

			load_addr = (uint32_t)hab_rvt_authenticate_image(
					HAB_CID_UBOOT,
					ivt_offset, (void **)&start,
					(size_t *)&bytes, NULL);
			if (hab_rvt_exit() != HAB_SUCCESS) {
				puts("hab exit function fail\n");
				load_addr = 0;
			}
		} else {
			puts("hab entry function fail\n");
		}

		hab_caam_clock_enable(0);

#if !defined(CONFIG_SPL_BUILD)
		get_hab_status();
#endif
	} else {
		puts("hab fuse not enabled\n");
	}

	if ((!is_hab_enabled()) || (load_addr != 0))
		result = 0;

	return result;
}
Commit	Line	Data
b83c709e	1	/*
29067abf	2	* Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
b83c709e SB	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
fba6f9ef AA	8	#include <config.h>
fba6f9ef AA	9	#include <fuse.h>
b83c709e	10	#include <asm/io.h>
36c1ca4d	11	#include <asm/system.h>
36c1ca4d	12	#include <asm/arch/clock.h>
f2f07e85	13	#include <asm/arch/sys_proto.h>
552a848e	14	#include <asm/mach-imx/hab.h>
b83c709e SB	15
b83c709e SB	16	/* -------- start of HAB API updates ------------*/
f2f07e85 SB	17
	18	#define hab_rvt_report_event_p \
	19	( \
b5437a80 PF	20	(is_mx6dqp()) ? \
b5437a80 PF	21	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
27cd0da4	22	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
f2f07e85	23	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
27cd0da4	24	(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
f2f07e85 SB	25	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
	26	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
	27	)
	28
	29	#define hab_rvt_report_status_p \
	30	( \
b5437a80 PF	31	(is_mx6dqp()) ? \
b5437a80 PF	32	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
27cd0da4	33	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
f2f07e85	34	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
27cd0da4	35	(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
f2f07e85 SB	36	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
	37	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
	38	)
	39
	40	#define hab_rvt_authenticate_image_p \
	41	( \
b5437a80 PF	42	(is_mx6dqp()) ? \
b5437a80 PF	43	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
27cd0da4	44	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
f2f07e85	45	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
27cd0da4	46	(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
f2f07e85 SB	47	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
	48	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
	49	)
	50
	51	#define hab_rvt_entry_p \
	52	( \
b5437a80 PF	53	(is_mx6dqp()) ? \
b5437a80 PF	54	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
27cd0da4	55	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
f2f07e85	56	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
27cd0da4	57	(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
f2f07e85 SB	58	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
	59	((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
	60	)
	61
	62	#define hab_rvt_exit_p \
	63	( \
b5437a80 PF	64	(is_mx6dqp()) ? \
b5437a80 PF	65	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
27cd0da4	66	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
f2f07e85	67	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
27cd0da4	68	(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
f2f07e85 SB	69	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
	70	((hab_rvt_exit_t *)HAB_RVT_EXIT) \
	71	)
b83c709e	72
36c1ca4d NG	73	#define IVT_SIZE 0x20
	74	#define ALIGN_SIZE 0x1000
	75	#define CSF_PAD_SIZE 0x2000
	76	#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
	77	#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
	78	#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
ee3899aa	79	#define IS_HAB_ENABLED_BIT \
27117b20 PF	80	(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
27117b20 PF	81	(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
36c1ca4d NG	82
	83	/*
	84	* +------------+ 0x0 (DDR_UIMAGE_START) -
	85	* \| Header \| \|
	86	* +------------+ 0x40 \|
	87	* \| \| \|
	88	* \| \| \|
	89	* \| \| \|
	90	* \| \| \|
	91	* \| Image Data \| \|
	92	* . \| \|
	93	* . \| > Stuff to be authenticated ----+
	94	* . \| \| \|
	95	* \| \| \| \|
	96	* \| \| \| \|
	97	* +------------+ \| \|
	98	* \| \| \| \|
	99	* \| Fill Data \| \| \|
	100	* \| \| \| \|
	101	* +------------+ Align to ALIGN_SIZE \| \|
	102	* \| IVT \| \| \|
	103	* +------------+ + IVT_SIZE - \|
	104	* \| \| \|
	105	* \| CSF DATA \| <---------------------------------------------------------+
	106	* \| \|
	107	* +------------+
	108	* \| \|
	109	* \| Fill Data \|
	110	* \| \|
	111	* +------------+ + CSF_PAD_SIZE
	112	*/
	113
15b505b0 SE	114	static bool is_hab_enabled(void);
	115
	116	#if !defined(CONFIG_SPL_BUILD)
	117
29067abf UC	118	#define MAX_RECORD_BYTES (81024) / 4 kbytes */
	119
	120	struct record {
	121	uint8_t tag; /* Tag */
	122	uint8_t len[2]; /* Length */
	123	uint8_t par; /* Version */
	124	uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
	125	bool any_rec_flag;
	126	};
	127
	128	char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
	129	"RSN = HAB_ENG_FAIL (0x30)\n",
	130	"RSN = HAB_INV_ADDRESS (0x22)\n",
	131	"RSN = HAB_INV_ASSERTION (0x0C)\n",
	132	"RSN = HAB_INV_CALL (0x28)\n",
	133	"RSN = HAB_INV_CERTIFICATE (0x21)\n",
	134	"RSN = HAB_INV_COMMAND (0x06)\n",
	135	"RSN = HAB_INV_CSF (0x11)\n",
	136	"RSN = HAB_INV_DCD (0x27)\n",
	137	"RSN = HAB_INV_INDEX (0x0F)\n",
	138	"RSN = HAB_INV_IVT (0x05)\n",
	139	"RSN = HAB_INV_KEY (0x1D)\n",
	140	"RSN = HAB_INV_RETURN (0x1E)\n",
	141	"RSN = HAB_INV_SIGNATURE (0x18)\n",
	142	"RSN = HAB_INV_SIZE (0x17)\n",
	143	"RSN = HAB_MEM_FAIL (0x2E)\n",
	144	"RSN = HAB_OVR_COUNT (0x2B)\n",
	145	"RSN = HAB_OVR_STORAGE (0x2D)\n",
	146	"RSN = HAB_UNS_ALGORITHM (0x12)\n",
	147	"RSN = HAB_UNS_COMMAND (0x03)\n",
	148	"RSN = HAB_UNS_ENGINE (0x0A)\n",
	149	"RSN = HAB_UNS_ITEM (0x24)\n",
	150	"RSN = HAB_UNS_KEY (0x1B)\n",
	151	"RSN = HAB_UNS_PROTOCOL (0x14)\n",
	152	"RSN = HAB_UNS_STATE (0x09)\n",
	153	"RSN = INVALID\n",
	154	NULL};
	155
	156	char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
	157	"STS = HAB_FAILURE (0x33)\n",
	158	"STS = HAB_WARNING (0x69)\n",
	159	"STS = INVALID\n",
	160	NULL};
	161
	162	char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
	163	"ENG = HAB_ENG_SCC (0x03)\n",
	164	"ENG = HAB_ENG_RTIC (0x05)\n",
	165	"ENG = HAB_ENG_SAHARA (0x06)\n",
	166	"ENG = HAB_ENG_CSU (0x0A)\n",
	167	"ENG = HAB_ENG_SRTC (0x0C)\n",
	168	"ENG = HAB_ENG_DCP (0x1B)\n",
	169	"ENG = HAB_ENG_CAAM (0x1D)\n",
	170	"ENG = HAB_ENG_SNVS (0x1E)\n",
	171	"ENG = HAB_ENG_OCOTP (0x21)\n",
	172	"ENG = HAB_ENG_DTCP (0x22)\n",
	173	"ENG = HAB_ENG_ROM (0x36)\n",
	174	"ENG = HAB_ENG_HDCP (0x24)\n",
	175	"ENG = HAB_ENG_RTL (0x77)\n",
	176	"ENG = HAB_ENG_SW (0xFF)\n",
	177	"ENG = INVALID\n",
	178	NULL};
	179
	180	char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
	181	"CTX = HAB_CTX_FAB (0xFF)\n",
182	"CTX = HAB_CTX_ENTRY (0xE1)\n",
183	"CTX = HAB_CTX_TARGET (0x33)\n",
184	"CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
185	"CTX = HAB_CTX_DCD (0xDD)\n",
186	"CTX = HAB_CTX_CSF (0xCF)\n",
187	"CTX = HAB_CTX_COMMAND (0xC0)\n",
188	"CTX = HAB_CTX_AUT_DAT (0xDB)\n",
189	"CTX = HAB_CTX_ASSERT (0xA0)\n",
190	"CTX = HAB_CTX_EXIT (0xEE)\n",
191	"CTX = INVALID\n",
192	NULL};
193
194	uint8_t hab_statuses[5] = {
195	HAB_STS_ANY,
196	HAB_FAILURE,
197	HAB_WARNING,
198	HAB_SUCCESS,
199	-1
200	};
201
202	uint8_t hab_reasons[26] = {
203	HAB_RSN_ANY,
204	HAB_ENG_FAIL,
205	HAB_INV_ADDRESS,
206	HAB_INV_ASSERTION,
207	HAB_INV_CALL,
208	HAB_INV_CERTIFICATE,
209	HAB_INV_COMMAND,
210	HAB_INV_CSF,
211	HAB_INV_DCD,
212	HAB_INV_INDEX,
213	HAB_INV_IVT,
214	HAB_INV_KEY,
215	HAB_INV_RETURN,
216	HAB_INV_SIGNATURE,
217	HAB_INV_SIZE,
218	HAB_MEM_FAIL,
219	HAB_OVR_COUNT,
220	HAB_OVR_STORAGE,
221	HAB_UNS_ALGORITHM,
222	HAB_UNS_COMMAND,
223	HAB_UNS_ENGINE,
224	HAB_UNS_ITEM,
225	HAB_UNS_KEY,
226	HAB_UNS_PROTOCOL,
227	HAB_UNS_STATE,
228	-1
229	};
230
231	uint8_t hab_contexts[12] = {
232	HAB_CTX_ANY,
233	HAB_CTX_FAB,
234	HAB_CTX_ENTRY,
235	HAB_CTX_TARGET,
236	HAB_CTX_AUTHENTICATE,
237	HAB_CTX_DCD,
238	HAB_CTX_CSF,
239	HAB_CTX_COMMAND,
240	HAB_CTX_AUT_DAT,
241	HAB_CTX_ASSERT,
242	HAB_CTX_EXIT,
243	-1
244	};
245
246	uint8_t hab_engines[16] = {
247	HAB_ENG_ANY,
248	HAB_ENG_SCC,
249	HAB_ENG_RTIC,
250	HAB_ENG_SAHARA,
251	HAB_ENG_CSU,
252	HAB_ENG_SRTC,
253	HAB_ENG_DCP,
254	HAB_ENG_CAAM,
255	HAB_ENG_SNVS,
256	HAB_ENG_OCOTP,
257	HAB_ENG_DTCP,
258	HAB_ENG_ROM,
259	HAB_ENG_HDCP,
260	HAB_ENG_RTL,
261	HAB_ENG_SW,
262	-1
263	};
264
29067abf UC	265	static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
	266	{
	267	uint8_t idx = 0;
	268	uint8_t element = list[idx];
	269	while (element != -1) {
	270	if (element == tgt)
	271	return idx;
	272	element = list[++idx];
	273	}
	274	return -1;
	275	}
	276
	277	void process_event_record(uint8_t *event_data, size_t bytes)
	278	{
	279	struct record rec = (struct record )event_data;
	280
	281	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
	282	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
	283	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
	284	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
	285	}
	286
b83c709e SB	287	void display_event(uint8_t *event_data, size_t bytes)
	288	{
	289	uint32_t i;
	290
	291	if (!(event_data && bytes > 0))
	292	return;
	293
	294	for (i = 0; i < bytes; i++) {
	295	if (i == 0)
	296	printf("\t0x%02x", event_data[i]);
	297	else if ((i % 8) == 0)
	298	printf("\n\t0x%02x", event_data[i]);
	299	else
	300	printf(" 0x%02x", event_data[i]);
	301	}
29067abf UC	302
29067abf UC	303	process_event_record(event_data, bytes);
b83c709e SB	304	}
	305
	306	int get_hab_status(void)
	307	{
	308	uint32_t index = 0; /* Loop index */
	309	uint8_t event_data[128]; /* Event data buffer */
	310	size_t bytes = sizeof(event_data); /* Event size in bytes */
	311	enum hab_config config = 0;
	312	enum hab_state state = 0;
f2f07e85 SB	313	hab_rvt_report_event_t *hab_rvt_report_event;
	314	hab_rvt_report_status_t *hab_rvt_report_status;
	315
	316	hab_rvt_report_event = hab_rvt_report_event_p;
	317	hab_rvt_report_status = hab_rvt_report_status_p;
b83c709e SB	318
	319	if (is_hab_enabled())
	320	puts("\nSecure boot enabled\n");
	321	else
	322	puts("\nSecure boot disabled\n");
	323
	324	/* Check HAB status */
	325	if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
	326	printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
	327	config, state);
	328
	329	/* Display HAB Error events */
	330	while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
	331	&bytes) == HAB_SUCCESS) {
	332	puts("\n");
	333	printf("--------- HAB Event %d -----------------\n",
	334	index + 1);
	335	puts("event data:\n");
	336	display_event(event_data, bytes);
	337	puts("\n");
	338	bytes = sizeof(event_data);
	339	index++;
	340	}
	341	}
	342	/* Display message if no HAB events are found */
	343	else {
	344	printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
	345	config, state);
	346	puts("No HAB Events Found!\n\n");
	347	}
	348	return 0;
	349	}
	350
15b505b0 SE	351	int do_hab_status(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	352	{
	353	if ((argc != 1)) {
	354	cmd_usage(cmdtp);
	355	return 1;
	356	}
	357
	358	get_hab_status();
	359
	360	return 0;
	361	}
	362
	363	static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
	364	char * const argv[])
	365	{
	366	ulong addr, ivt_offset;
	367	int rcode = 0;
	368
	369	if (argc < 3)
	370	return CMD_RET_USAGE;
	371
	372	addr = simple_strtoul(argv[1], NULL, 16);
	373	ivt_offset = simple_strtoul(argv[2], NULL, 16);
	374
	375	rcode = authenticate_image(addr, ivt_offset);
9535b397 BD	376	if (rcode == 0)
	377	rcode = CMD_RET_SUCCESS;
	378	else
	379	rcode = CMD_RET_FAILURE;
15b505b0 SE	380	return rcode;
	381	}
	382
	383	U_BOOT_CMD(
	384	hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
	385	"display HAB status",
	386	""
	387	);
	388
	389	U_BOOT_CMD(
	390	hab_auth_img, 3, 0, do_authenticate_image,
	391	"authenticate image via HAB",
	392	"addr ivt_offset\n"
	393	"addr - image hex address\n"
	394	"ivt_offset - hex offset of IVT in the image"
	395	);
	396
	397
	398	#endif /* !defined(CONFIG_SPL_BUILD) */
	399
	400	static bool is_hab_enabled(void)
	401	{
	402	struct imx_sec_config_fuse_t *fuse =
	403	(struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
	404	uint32_t reg;
	405	int ret;
	406
	407	ret = fuse_read(fuse->bank, fuse->word, &reg);
	408	if (ret) {
	409	puts("\nSecure boot fuse read error\n");
	410	return ret;
	411	}
	412
	413	return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
	414	}
	415
adbb051f	416	int authenticate_image(uint32_t ddr_start, uint32_t image_size)
36c1ca4d NG	417	{
	418	uint32_t load_addr = 0;
	419	size_t bytes;
	420	ptrdiff_t ivt_offset = 0;
9535b397	421	int result = 1;
36c1ca4d NG	422	ulong start;
	423	hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
	424	hab_rvt_entry_t *hab_rvt_entry;
	425	hab_rvt_exit_t *hab_rvt_exit;
	426
	427	hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
	428	hab_rvt_entry = hab_rvt_entry_p;
	429	hab_rvt_exit = hab_rvt_exit_p;
	430
	431	if (is_hab_enabled()) {
	432	printf("\nAuthenticate image from DDR location 0x%x...\n",
	433	ddr_start);
	434
	435	hab_caam_clock_enable(1);
	436
	437	if (hab_rvt_entry() == HAB_SUCCESS) {
	438	/* If not already aligned, Align to ALIGN_SIZE */
	439	ivt_offset = (image_size + ALIGN_SIZE - 1) &
	440	~(ALIGN_SIZE - 1);
	441
	442	start = ddr_start;
	443	bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
	444	#ifdef DEBUG
	445	printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
	446	ivt_offset, ddr_start + ivt_offset);
	447	puts("Dumping IVT\n");
	448	print_buffer(ddr_start + ivt_offset,
	449	(void *)(ddr_start + ivt_offset),
	450	4, 0x8, 0);
	451
	452	puts("Dumping CSF Header\n");
	453	print_buffer(ddr_start + ivt_offset+IVT_SIZE,
	454	(void *)(ddr_start + ivt_offset+IVT_SIZE),
	455	4, 0x10, 0);
	456
15b505b0	457	#if !defined(CONFIG_SPL_BUILD)
36c1ca4d	458	get_hab_status();
15b505b0	459	#endif
36c1ca4d NG	460
	461	puts("\nCalling authenticate_image in ROM\n");
	462	printf("\tivt_offset = 0x%x\n", ivt_offset);
	463	printf("\tstart = 0x%08lx\n", start);
	464	printf("\tbytes = 0x%x\n", bytes);
	465	#endif
	466	/*
	467	* If the MMU is enabled, we have to notify the ROM
	468	* code, or it won't flush the caches when needed.
	469	* This is done, by setting the "pu_irom_mmu_enabled"
	470	* word to 1. You can find its address by looking in
	471	* the ROM map. This is critical for
	472	* authenticate_image(). If MMU is enabled, without
	473	* setting this bit, authentication will fail and may
	474	* crash.
	475	*/
	476	/* Check MMU enabled */
ee3899aa	477	if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
27cd0da4	478	if (is_mx6dq()) {
36c1ca4d NG	479	/*
	480	* This won't work on Rev 1.0.0 of
	481	* i.MX6Q/D, since their ROM doesn't
	482	* do cache flushes. don't think any
	483	* exist, so we ignore them.
	484	*/
ec0f9530 YL	485	if (!is_mx6dqp())
ec0f9530 YL	486	writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
27cd0da4	487	} else if (is_mx6sdl()) {
36c1ca4d	488	writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
27cd0da4	489	} else if (is_mx6sl()) {
36c1ca4d NG	490	writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
	491	}
	492	}
	493
	494	load_addr = (uint32_t)hab_rvt_authenticate_image(
	495	HAB_CID_UBOOT,
	496	ivt_offset, (void **)&start,
	497	(size_t *)&bytes, NULL);
	498	if (hab_rvt_exit() != HAB_SUCCESS) {
	499	puts("hab exit function fail\n");
	500	load_addr = 0;
	501	}
	502	} else {
	503	puts("hab entry function fail\n");
	504	}
	505
	506	hab_caam_clock_enable(0);
	507
15b505b0	508	#if !defined(CONFIG_SPL_BUILD)
36c1ca4d	509	get_hab_status();
15b505b0	510	#endif
36c1ca4d NG	511	} else {
	512	puts("hab fuse not enabled\n");
	513	}
	514
	515	if ((!is_hab_enabled()) \|\| (load_addr != 0))
9535b397	516	result = 0;
36c1ca4d NG	517
	518	return result;
	519	}