[people/ms/u-boot.git] / arch / arm / mach-imx / misc.c

/*
 * Copyright 2013 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/mach-imx/regs-common.h>

/* 1 second delay should be plenty of time for block reset. */
#define	RESET_MAX_TIMEOUT	1000000

#define	MXS_BLOCK_SFTRST	(1 << 31)
#define	MXS_BLOCK_CLKGATE	(1 << 30)

int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
								int timeout)
{
	while (--timeout) {
		if ((readl(&reg->reg) & mask) == mask)
			break;
		udelay(1);
	}

	return !timeout;
}

int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
								int timeout)
{
	while (--timeout) {
		if ((readl(&reg->reg) & mask) == 0)
			break;
		udelay(1);
	}

	return !timeout;
}

int mxs_reset_block(struct mxs_register_32 *reg)
{
	/* Clear SFTRST */
	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);

	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
		return 1;

	/* Clear CLKGATE */
	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);

	/* Set SFTRST */
	writel(MXS_BLOCK_SFTRST, &reg->reg_set);

	/* Wait for CLKGATE being set */
	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
		return 1;

	/* Clear SFTRST */
	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);

	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
		return 1;

	/* Clear CLKGATE */
	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);

	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
		return 1;

	return 0;
}
Commit	Line	Data
8870e459 SR	1	/*
	2	* Copyright 2013 Stefan Roese <sr@denx.de>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
8870e459 SR	5	*/
	6
	7	#include <common.h>
5624c6bd	8	#include <asm/arch/sys_proto.h>
1221ce45	9	#include <linux/errno.h>
8870e459	10	#include <asm/io.h>
552a848e	11	#include <asm/mach-imx/regs-common.h>
8870e459 SR	12
	13	/* 1 second delay should be plenty of time for block reset. */
	14	#define RESET_MAX_TIMEOUT 1000000
	15
	16	#define MXS_BLOCK_SFTRST (1 << 31)
	17	#define MXS_BLOCK_CLKGATE (1 << 30)
	18
	19	int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
	20	int timeout)
	21	{
	22	while (--timeout) {
	23	if ((readl(&reg->reg) & mask) == mask)
	24	break;
	25	udelay(1);
	26	}
	27
	28	return !timeout;
	29	}
	30
	31	int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
	32	int timeout)
	33	{
	34	while (--timeout) {
	35	if ((readl(&reg->reg) & mask) == 0)
	36	break;
	37	udelay(1);
	38	}
	39
	40	return !timeout;
	41	}
	42
	43	int mxs_reset_block(struct mxs_register_32 *reg)
	44	{
	45	/* Clear SFTRST */
	46	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
	47
	48	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
	49	return 1;
	50
	51	/* Clear CLKGATE */
	52	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
	53
	54	/* Set SFTRST */
	55	writel(MXS_BLOCK_SFTRST, &reg->reg_set);
	56
	57	/* Wait for CLKGATE being set */
	58	if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
	59	return 1;
	60
	61	/* Clear SFTRST */
	62	writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
	63
	64	if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
	65	return 1;
	66
	67	/* Clear CLKGATE */
	68	writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
	69
	70	if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
	71	return 1;
	72
	73	return 0;
	74	}