[people/ms/u-boot.git] / arch / arm / mach-imx / mx5 / lowlevel_init.S

/*
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <linux/linkage.h>

.section ".text.init", "x"

.macro init_arm_erratum
	/* ARM erratum ID #468414 */
	mrc 15, 0, r1, c1, c0, 1
	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
	mcr 15, 0, r1, c1, c0, 1
.endm

/*
 * L2CC Cache setup/invalidation/disable
 */
.macro init_l2cc
	/* explicitly disable L2 cache */
	mrc 15, 0, r0, c1, c0, 1
	bic r0, r0, #0x2
	mcr 15, 0, r0, c1, c0, 1

	/* reconfigure L2 cache aux control reg */
	ldr r0, =0xC0 |			/* tag RAM */ \
		 0x4 |			/* data RAM */ \
		 1 << 24 |		/* disable write allocate delay */ \
		 1 << 23 |		/* disable write allocate combine */ \
		 1 << 22		/* disable write allocate */

#if defined(CONFIG_MX51)
	ldr r3, [r4, #ROM_SI_REV]
	cmp r3, #0x10

	/* disable write combine for TO 2 and lower revs */
	orrls r0, r0, #1 << 25
#endif

	mcr 15, 1, r0, c9, c0, 2

	/* enable L2 cache */
	mrc 15, 0, r0, c1, c0, 1
	orr r0, r0, #2
	mcr 15, 0, r0, c1, c0, 1

.endm /* init_l2cc */

/* AIPS setup - Only setup MPROTx registers.
 * The PACR default values are good.*/
.macro init_aips
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	ldr r0, =AIPS1_BASE_ADDR
	ldr r1, =0x77777777
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	ldr r0, =AIPS2_BASE_ADDR
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	/*
	 * Clear the on and off peripheral modules Supervisor Protect bit
	 * for SDMA to access them. Did not change the AIPS control registers
	 * (offset 0x20) access type
	 */
.endm /* init_aips */

/* M4IF setup */
.macro init_m4if
#ifdef CONFIG_MX51
	/* VPU and IPU given higher priority (0x4)
	 * IPU accesses with ID=0x1 given highest priority (=0xA)
	 */
	ldr r0, =M4IF_BASE_ADDR

	ldr r1, =0x00000203
	str r1, [r0, #0x40]

	str r4, [r0, #0x44]

	ldr r1, =0x00120125
	str r1, [r0, #0x9C]

	ldr r1, =0x001901A3
	str r1, [r0, #0x48]

#endif
.endm /* init_m4if */

.macro setup_pll pll, freq
	ldr r0, =\pll
	adr r2, W_DP_\freq
	bl setup_pll_func
.endm

#define W_DP_OP		0
#define W_DP_MFD	4
#define W_DP_MFN	8

setup_pll_func:
	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
	mov r1, #0x2
	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */

	ldr r1, [r2, #W_DP_OP]
	str r1, [r0, #PLL_DP_OP]
	str r1, [r0, #PLL_DP_HFS_OP]

	ldr r1, [r2, #W_DP_MFD]
	str r1, [r0, #PLL_DP_MFD]
	str r1, [r0, #PLL_DP_HFS_MFD]

	ldr r1, [r2, #W_DP_MFN]
	str r1, [r0, #PLL_DP_MFN]
	str r1, [r0, #PLL_DP_HFS_MFN]

	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL]
1:	ldr r1, [r0, #PLL_DP_CTL]
	ands r1, r1, #0x1
	beq 1b

	/* r10 saved upper lr */
	mov pc, lr

.macro setup_pll_errata pll, freq
	ldr r2, =\pll
	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
	ldr r1, =0x00001236
	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
	ands r1, r1, #0x1
	beq 1b

	ldr r5, \freq
	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
	str r5, [r2, #PLL_DP_HFS_MFN]

	mov r1, #0x1
	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */

2:	ldr r1, [r2, #PLL_DP_CONFIG]
	tst r1, #1
	bne 2b

	ldr r1, =100		     /* Wait at least 4 us */
3:	subs r1, r1, #1
	bge 3b

	mov r1, #0x2
	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
.endm

.macro init_clock
#if defined (CONFIG_MX51)
	ldr r0, =CCM_BASE_ADDR

	/* Gate of clocks to the peripherals first */
	ldr r1, =0x3FFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r4, [r0, #CLKCTL_CCGR1]
	str r4, [r0, #CLKCTL_CCGR2]
	str r4, [r0, #CLKCTL_CCGR3]

	ldr r1, =0x00030000
	str r1, [r0, #CLKCTL_CCGR4]
	ldr r1, =0x00FFF030
	str r1, [r0, #CLKCTL_CCGR5]
	ldr r1, =0x00000300
	str r1, [r0, #CLKCTL_CCGR6]

	/* Disable IPU and HSC dividers */
	mov r1, #0x60000
	str r1, [r0, #CLKCTL_CCDR]

	/* Make sure to switch the DDR away from PLL 1 */
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	/* Switch ARM to step clock */
	mov r1, #0x4
	str r1, [r0, #CLKCTL_CCSR]

#if defined(CONFIG_MX51_PLL_ERRATA)
	setup_pll PLL1_BASE_ADDR, 864
	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
	setup_pll PLL1_BASE_ADDR, 800
#endif

	setup_pll PLL3_BASE_ADDR, 665

	/* Switch peripheral to PLL 3 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	ldr r1, =0x13239145
	str r1, [r0, #CLKCTL_CBCDR]
	setup_pll PLL2_BASE_ADDR, 665

	/* Switch peripheral to PLL2 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]

	setup_pll PLL3_BASE_ADDR, 216

	/* Set the platform clock dividers */
	ldr r0, =ARM_BASE_ADDR
	ldr r1, =0x00000725
	str r1, [r0, #0x14]

	ldr r0, =CCM_BASE_ADDR

	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
	ldr r3, [r4, #ROM_SI_REV]
	cmp r3, #0x10
	movls r1, #0x1
	movhi r1, #0

	str r1, [r0, #CLKCTL_CACRR]

	/* Switch ARM back to PLL 1 */
	str r4, [r0, #CLKCTL_CCSR]

	/* setup the rest */
	/* Use lp_apm (24MHz) source for perclk */
	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
	str r1, [r0, #CLKCTL_CBCDR]

	/* Restore the default values in the Gate registers */
	ldr r1, =0xFFFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]
	str r1, [r0, #CLKCTL_CCGR4]
	str r1, [r0, #CLKCTL_CCGR5]
	str r1, [r0, #CLKCTL_CCGR6]

	/* Use PLL 2 for UART's, get 66.5MHz from it */
	ldr r1, =0xA5A2A020
	str r1, [r0, #CLKCTL_CSCMR1]
	ldr r1, =0x00C30321
	str r1, [r0, #CLKCTL_CSCDR1]
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	str r4, [r0, #CLKCTL_CCDR]

	/* for cko - for ARM div by 8 */
	mov r1, #0x000A0000
	add r1, r1, #0x00000F0
	str r1, [r0, #CLKCTL_CCOSR]
#else	/* CONFIG_MX53 */
	ldr r0, =CCM_BASE_ADDR

	/* Gate of clocks to the peripherals first */
	ldr r1, =0x3FFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r4, [r0, #CLKCTL_CCGR1]
	str r4, [r0, #CLKCTL_CCGR2]
	str r4, [r0, #CLKCTL_CCGR3]
	str r4, [r0, #CLKCTL_CCGR7]
	ldr r1, =0x00030000
	str r1, [r0, #CLKCTL_CCGR4]
	ldr r1, =0x00FFF030
	str r1, [r0, #CLKCTL_CCGR5]
	ldr r1, =0x0F00030F
	str r1, [r0, #CLKCTL_CCGR6]

	/* Switch ARM to step clock */
	mov r1, #0x4
	str r1, [r0, #CLKCTL_CCSR]

	setup_pll PLL1_BASE_ADDR, 800

	setup_pll PLL3_BASE_ADDR, 400

	/* Switch peripheral to PLL3 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x00015154
	str r1, [r0, #CLKCTL_CBCMR]
	ldr r1, =0x02898945
	str r1, [r0, #CLKCTL_CBCDR]
	/* make sure change is effective */
1:      ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	setup_pll PLL2_BASE_ADDR, 400

	/* Switch peripheral to PLL2 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x00888945
	str r1, [r0, #CLKCTL_CBCDR]

	ldr r1, =0x00016154
	str r1, [r0, #CLKCTL_CBCMR]

	/*change uart clk parent to pll2*/
	ldr r1, [r0, #CLKCTL_CSCMR1]
	and r1, r1, #0xfcffffff
	orr r1, r1, #0x01000000
	str r1, [r0, #CLKCTL_CSCMR1]

	/* make sure change is effective */
1:      ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	setup_pll PLL3_BASE_ADDR, 216

	setup_pll PLL4_BASE_ADDR, 455

	/* Set the platform clock dividers */
	ldr r0, =ARM_BASE_ADDR
	ldr r1, =0x00000124
	str r1, [r0, #0x14]

	ldr r0, =CCM_BASE_ADDR
	mov r1, #0
	str r1, [r0, #CLKCTL_CACRR]

	/* Switch ARM back to PLL 1. */
	mov r1, #0x0
	str r1, [r0, #CLKCTL_CCSR]

	/* make uart div=6 */
	ldr r1, [r0, #CLKCTL_CSCDR1]
	and r1, r1, #0xffffffc0
	orr r1, r1, #0x0a
	str r1, [r0, #CLKCTL_CSCDR1]

	/* Restore the default values in the Gate registers */
	ldr r1, =0xFFFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]
	str r1, [r0, #CLKCTL_CCGR4]
	str r1, [r0, #CLKCTL_CCGR5]
	str r1, [r0, #CLKCTL_CCGR6]
	str r1, [r0, #CLKCTL_CCGR7]

	mov r1, #0x00000
	str r1, [r0, #CLKCTL_CCDR]

	/* for cko - for ARM div by 8 */
	mov r1, #0x000A0000
	add r1, r1, #0x00000F0
	str r1, [r0, #CLKCTL_CCOSR]

#endif	/* CONFIG_MX53 */
.endm

ENTRY(lowlevel_init)
	mov r10, lr
	mov r4, #0	/* Fix R4 to 0 */

#if defined(CONFIG_SYS_MAIN_PWR_ON)
	ldr r0, =GPIO1_BASE_ADDR
	ldr r1, [r0, #0x0]
	orr r1, r1, #1 << 23
	str r1, [r0, #0x0]
	ldr r1, [r0, #0x4]
	orr r1, r1, #1 << 23
	str r1, [r0, #0x4]
#endif

	init_arm_erratum

	init_l2cc

	init_aips

	init_m4if

	init_clock

	mov pc, r10
ENDPROC(lowlevel_init)

/* Board level setting value */
#if defined(CONFIG_MX51_PLL_ERRATA)
W_DP_864:		.word DP_OP_864
			.word DP_MFD_864
			.word DP_MFN_864
W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
#else
W_DP_800:		.word DP_OP_800
			.word DP_MFD_800
			.word DP_MFN_800
#endif
#if defined(CONFIG_MX51)
W_DP_665:		.word DP_OP_665
			.word DP_MFD_665
			.word DP_MFN_665
#endif
W_DP_216:		.word DP_OP_216
			.word DP_MFD_216
			.word DP_MFN_216
W_DP_400:               .word DP_OP_400
			.word DP_MFD_400
			.word DP_MFN_400
W_DP_455:               .word DP_OP_455
			.word DP_MFD_455
			.word DP_MFN_455
Commit	Line	Data
64fdf452 SB	1	/*
	2	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
64fdf452 SB	7	*/
	8
	9	#include <config.h>
	10	#include <asm/arch/imx-regs.h>
a4814a69	11	#include <generated/asm-offsets.h>
74236aca	12	#include <linux/linkage.h>
64fdf452	13
dd227b6e BT	14	.section ".text.init", "x"
dd227b6e BT	15
c4fe17f6 FE	16	.macro init_arm_erratum
	17	/* ARM erratum ID #468414 */
	18	mrc 15, 0, r1, c1, c0, 1
	19	orr r1, r1, #(1 << 5) /* enable L1NEON bit */
	20	mcr 15, 0, r1, c1, c0, 1
	21	.endm
	22
64fdf452 SB	23	/*
	24	* L2CC Cache setup/invalidation/disable
	25	*/
	26	.macro init_l2cc
	27	/* explicitly disable L2 cache */
	28	mrc 15, 0, r0, c1, c0, 1
	29	bic r0, r0, #0x2
	30	mcr 15, 0, r0, c1, c0, 1
	31
	32	/* reconfigure L2 cache aux control reg */
dd227b6e	33	ldr r0, =0xC0 \| /* tag RAM */ \
93e14596 WD	34	0x4 \| /* data RAM */ \
	35	1 << 24 \| /* disable write allocate delay */ \
	36	1 << 23 \| /* disable write allocate combine */ \
	37	1 << 22 /* disable write allocate */
64fdf452	38
6e25b6ce	39	#if defined(CONFIG_MX51)
dd227b6e	40	ldr r3, [r4, #ROM_SI_REV]
6e25b6ce	41	cmp r3, #0x10
64fdf452 SB	42
64fdf452 SB	43	/* disable write combine for TO 2 and lower revs */
18c63990	44	orrls r0, r0, #1 << 25
6e25b6ce	45	#endif
64fdf452 SB	46
64fdf452 SB	47	mcr 15, 1, r0, c9, c0, 2
4867b634 FE	48
	49	/* enable L2 cache */
	50	mrc 15, 0, r0, c1, c0, 1
	51	orr r0, r0, #2
	52	mcr 15, 0, r0, c1, c0, 1
	53
64fdf452 SB	54	.endm /* init_l2cc */
	55
	56	/* AIPS setup - Only setup MPROTx registers.
	57	* The PACR default values are good.*/
	58	.macro init_aips
	59	/*
	60	* Set all MPROTx to be non-bufferable, trusted for R/W,
	61	* not forced to user-mode.
	62	*/
	63	ldr r0, =AIPS1_BASE_ADDR
	64	ldr r1, =0x77777777
	65	str r1, [r0, #0x0]
	66	str r1, [r0, #0x4]
	67	ldr r0, =AIPS2_BASE_ADDR
	68	str r1, [r0, #0x0]
	69	str r1, [r0, #0x4]
	70	/*
	71	* Clear the on and off peripheral modules Supervisor Protect bit
	72	* for SDMA to access them. Did not change the AIPS control registers
	73	* (offset 0x20) access type
	74	*/
	75	.endm /* init_aips */
	76
	77	/* M4IF setup */
	78	.macro init_m4if
595f3e56	79	#ifdef CONFIG_MX51
64fdf452 SB	80	/* VPU and IPU given higher priority (0x4)
	81	* IPU accesses with ID=0x1 given highest priority (=0xA)
	82	*/
	83	ldr r0, =M4IF_BASE_ADDR
	84
	85	ldr r1, =0x00000203
	86	str r1, [r0, #0x40]
	87
dd227b6e	88	str r4, [r0, #0x44]
64fdf452 SB	89
	90	ldr r1, =0x00120125
	91	str r1, [r0, #0x9C]
	92
	93	ldr r1, =0x001901A3
	94	str r1, [r0, #0x48]
	95
595f3e56	96	#endif
64fdf452 SB	97	.endm /* init_m4if */
	98
	99	.macro setup_pll pll, freq
595f3e56	100	ldr r0, =\pll
dd227b6e BT	101	adr r2, W_DP_\freq
	102	bl setup_pll_func
	103	.endm
	104
	105	#define W_DP_OP 0
	106	#define W_DP_MFD 4
	107	#define W_DP_MFN 8
	108
	109	setup_pll_func:
64fdf452	110	ldr r1, =0x00001232
595f3e56	111	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
64fdf452	112	mov r1, #0x2
595f3e56	113	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
64fdf452	114
dd227b6e	115	ldr r1, [r2, #W_DP_OP]
595f3e56 LHR	116	str r1, [r0, #PLL_DP_OP]
595f3e56 LHR	117	str r1, [r0, #PLL_DP_HFS_OP]
64fdf452	118
dd227b6e	119	ldr r1, [r2, #W_DP_MFD]
595f3e56 LHR	120	str r1, [r0, #PLL_DP_MFD]
595f3e56 LHR	121	str r1, [r0, #PLL_DP_HFS_MFD]
64fdf452	122
dd227b6e	123	ldr r1, [r2, #W_DP_MFN]
595f3e56 LHR	124	str r1, [r0, #PLL_DP_MFN]
595f3e56 LHR	125	str r1, [r0, #PLL_DP_HFS_MFN]
64fdf452 SB	126
64fdf452 SB	127	ldr r1, =0x00001232
595f3e56 LHR	128	str r1, [r0, #PLL_DP_CTL]
595f3e56 LHR	129	1: ldr r1, [r0, #PLL_DP_CTL]
64fdf452 SB	130	ands r1, r1, #0x1
64fdf452 SB	131	beq 1b
dd227b6e BT	132
	133	/* r10 saved upper lr */
	134	mov pc, lr
64fdf452	135
9db1bfa1 DJ	136	.macro setup_pll_errata pll, freq
9db1bfa1 DJ	137	ldr r2, =\pll
dd227b6e	138	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
9db1bfa1 DJ	139	ldr r1, =0x00001236
	140	str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
	141	1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
	142	ands r1, r1, #0x1
	143	beq 1b
	144
	145	ldr r5, \freq
	146	str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
	147	str r5, [r2, #PLL_DP_HFS_MFN]
	148
	149	mov r1, #0x1
	150	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
	151
	152	2: ldr r1, [r2, #PLL_DP_CONFIG]
	153	tst r1, #1
	154	bne 2b
	155
	156	ldr r1, =100 /* Wait at least 4 us */
	157	3: subs r1, r1, #1
	158	bge 3b
	159
	160	mov r1, #0x2
	161	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
	162	.endm
	163
64fdf452	164	.macro init_clock
758c3449	165	#if defined (CONFIG_MX51)
64fdf452 SB	166	ldr r0, =CCM_BASE_ADDR
	167
	168	/* Gate of clocks to the peripherals first */
	169	ldr r1, =0x3FFFFFFF
	170	str r1, [r0, #CLKCTL_CCGR0]
dd227b6e BT	171	str r4, [r0, #CLKCTL_CCGR1]
	172	str r4, [r0, #CLKCTL_CCGR2]
	173	str r4, [r0, #CLKCTL_CCGR3]
64fdf452 SB	174
	175	ldr r1, =0x00030000
	176	str r1, [r0, #CLKCTL_CCGR4]
	177	ldr r1, =0x00FFF030
	178	str r1, [r0, #CLKCTL_CCGR5]
	179	ldr r1, =0x00000300
	180	str r1, [r0, #CLKCTL_CCGR6]
	181
	182	/* Disable IPU and HSC dividers */
	183	mov r1, #0x60000
	184	str r1, [r0, #CLKCTL_CCDR]
	185
	186	/* Make sure to switch the DDR away from PLL 1 */
	187	ldr r1, =0x19239145
	188	str r1, [r0, #CLKCTL_CBCDR]
	189	/* make sure divider effective */
	190	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	191	cmp r1, #0x0
	192	bne 1b
	193
	194	/* Switch ARM to step clock */
	195	mov r1, #0x4
	196	str r1, [r0, #CLKCTL_CCSR]
64fdf452	197
9db1bfa1 DJ	198	#if defined(CONFIG_MX51_PLL_ERRATA)
	199	setup_pll PLL1_BASE_ADDR, 864
	200	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
	201	#else
595f3e56	202	setup_pll PLL1_BASE_ADDR, 800
9db1bfa1	203	#endif
595f3e56	204
595f3e56	205	setup_pll PLL3_BASE_ADDR, 665
64fdf452 SB	206
	207	/* Switch peripheral to PLL 3 */
	208	ldr r0, =CCM_BASE_ADDR
dd227b6e	209	ldr r1, =0x000010C0 \| CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	210	str r1, [r0, #CLKCTL_CBCMR]
	211	ldr r1, =0x13239145
	212	str r1, [r0, #CLKCTL_CBCDR]
595f3e56	213	setup_pll PLL2_BASE_ADDR, 665
64fdf452 SB	214
	215	/* Switch peripheral to PLL2 */
	216	ldr r0, =CCM_BASE_ADDR
	217	ldr r1, =0x19239145
	218	str r1, [r0, #CLKCTL_CBCDR]
dd227b6e	219	ldr r1, =0x000020C0 \| CONFIG_SYS_DDR_CLKSEL
64fdf452	220	str r1, [r0, #CLKCTL_CBCMR]
758c3449	221
595f3e56	222	setup_pll PLL3_BASE_ADDR, 216
64fdf452 SB	223
	224	/* Set the platform clock dividers */
	225	ldr r0, =ARM_BASE_ADDR
	226	ldr r1, =0x00000725
	227	str r1, [r0, #0x14]
	228
	229	ldr r0, =CCM_BASE_ADDR
	230
	231	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
dd227b6e	232	ldr r3, [r4, #ROM_SI_REV]
64fdf452 SB	233	cmp r3, #0x10
	234	movls r1, #0x1
	235	movhi r1, #0
758c3449	236
595f3e56	237	str r1, [r0, #CLKCTL_CACRR]
18c63990	238
64fdf452	239	/* Switch ARM back to PLL 1 */
dd227b6e	240	str r4, [r0, #CLKCTL_CCSR]
64fdf452 SB	241
	242	/* setup the rest */
	243	/* Use lp_apm (24MHz) source for perclk */
dd227b6e	244	ldr r1, =0x000020C2 \| CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	245	str r1, [r0, #CLKCTL_CBCMR]
64fdf452 SB	246	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
5e1fe88f	247	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
64fdf452 SB	248	str r1, [r0, #CLKCTL_CBCDR]
	249
	250	/* Restore the default values in the Gate registers */
	251	ldr r1, =0xFFFFFFFF
	252	str r1, [r0, #CLKCTL_CCGR0]
	253	str r1, [r0, #CLKCTL_CCGR1]
	254	str r1, [r0, #CLKCTL_CCGR2]
	255	str r1, [r0, #CLKCTL_CCGR3]
	256	str r1, [r0, #CLKCTL_CCGR4]
	257	str r1, [r0, #CLKCTL_CCGR5]
	258	str r1, [r0, #CLKCTL_CCGR6]
	259
	260	/* Use PLL 2 for UART's, get 66.5MHz from it */
	261	ldr r1, =0xA5A2A020
	262	str r1, [r0, #CLKCTL_CSCMR1]
	263	ldr r1, =0x00C30321
	264	str r1, [r0, #CLKCTL_CSCDR1]
758c3449 FE	265	/* make sure divider effective */
	266	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	267	cmp r1, #0x0
	268	bne 1b
	269
	270	str r4, [r0, #CLKCTL_CCDR]
	271
	272	/* for cko - for ARM div by 8 */
	273	mov r1, #0x000A0000
	274	add r1, r1, #0x00000F0
	275	str r1, [r0, #CLKCTL_CCOSR]
	276	#else /* CONFIG_MX53 */
	277	ldr r0, =CCM_BASE_ADDR
	278
	279	/* Gate of clocks to the peripherals first */
	280	ldr r1, =0x3FFFFFFF
	281	str r1, [r0, #CLKCTL_CCGR0]
	282	str r4, [r0, #CLKCTL_CCGR1]
	283	str r4, [r0, #CLKCTL_CCGR2]
	284	str r4, [r0, #CLKCTL_CCGR3]
	285	str r4, [r0, #CLKCTL_CCGR7]
	286	ldr r1, =0x00030000
	287	str r1, [r0, #CLKCTL_CCGR4]
	288	ldr r1, =0x00FFF030
	289	str r1, [r0, #CLKCTL_CCGR5]
	290	ldr r1, =0x0F00030F
	291	str r1, [r0, #CLKCTL_CCGR6]
	292
	293	/* Switch ARM to step clock */
	294	mov r1, #0x4
	295	str r1, [r0, #CLKCTL_CCSR]
	296
	297	setup_pll PLL1_BASE_ADDR, 800
	298
93e14596	299	setup_pll PLL3_BASE_ADDR, 400
782b0288	300
93e14596 WD	301	/* Switch peripheral to PLL3 */
	302	ldr r0, =CCM_BASE_ADDR
	303	ldr r1, =0x00015154
	304	str r1, [r0, #CLKCTL_CBCMR]
	305	ldr r1, =0x02898945
	306	str r1, [r0, #CLKCTL_CBCDR]
	307	/* make sure change is effective */
782b0288	308	1: ldr r1, [r0, #CLKCTL_CDHIPR]
93e14596 WD	309	cmp r1, #0x0
93e14596 WD	310	bne 1b
782b0288	311
93e14596	312	setup_pll PLL2_BASE_ADDR, 400
782b0288 FE	313
	314	/* Switch peripheral to PLL2 */
	315	ldr r0, =CCM_BASE_ADDR
e78b1408	316	ldr r1, =0x00888945
782b0288 FE	317	str r1, [r0, #CLKCTL_CBCDR]
	318
	319	ldr r1, =0x00016154
	320	str r1, [r0, #CLKCTL_CBCMR]
	321
	322	/change uart clk parent to pll2/
	323	ldr r1, [r0, #CLKCTL_CSCMR1]
	324	and r1, r1, #0xfcffffff
	325	orr r1, r1, #0x01000000
	326	str r1, [r0, #CLKCTL_CSCMR1]
	327
	328	/* make sure change is effective */
	329	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	330	cmp r1, #0x0
	331	bne 1b
	332
93e14596	333	setup_pll PLL3_BASE_ADDR, 216
782b0288 FE	334
782b0288 FE	335	setup_pll PLL4_BASE_ADDR, 455
758c3449 FE	336
	337	/* Set the platform clock dividers */
	338	ldr r0, =ARM_BASE_ADDR
782b0288	339	ldr r1, =0x00000124
758c3449 FE	340	str r1, [r0, #0x14]
	341
	342	ldr r0, =CCM_BASE_ADDR
758c3449 FE	343	mov r1, #0
	344	str r1, [r0, #CLKCTL_CACRR]
	345
782b0288 FE	346	/* Switch ARM back to PLL 1. */
	347	mov r1, #0x0
	348	str r1, [r0, #CLKCTL_CCSR]
	349
	350	/* make uart div=6 */
	351	ldr r1, [r0, #CLKCTL_CSCDR1]
	352	and r1, r1, #0xffffffc0
	353	orr r1, r1, #0x0a
	354	str r1, [r0, #CLKCTL_CSCDR1]
758c3449 FE	355
	356	/* Restore the default values in the Gate registers */
	357	ldr r1, =0xFFFFFFFF
	358	str r1, [r0, #CLKCTL_CCGR0]
	359	str r1, [r0, #CLKCTL_CCGR1]
	360	str r1, [r0, #CLKCTL_CCGR2]
	361	str r1, [r0, #CLKCTL_CCGR3]
	362	str r1, [r0, #CLKCTL_CCGR4]
	363	str r1, [r0, #CLKCTL_CCGR5]
	364	str r1, [r0, #CLKCTL_CCGR6]
	365	str r1, [r0, #CLKCTL_CCGR7]
	366
93e14596 WD	367	mov r1, #0x00000
93e14596 WD	368	str r1, [r0, #CLKCTL_CCDR]
67ee3dd3	369
93e14596 WD	370	/* for cko - for ARM div by 8 */
	371	mov r1, #0x000A0000
	372	add r1, r1, #0x00000F0
	373	str r1, [r0, #CLKCTL_CCOSR]
64fdf452	374
758c3449	375	#endif /* CONFIG_MX53 */
64fdf452 SB	376	.endm
64fdf452 SB	377
74236aca	378	ENTRY(lowlevel_init)
dd227b6e BT	379	mov r10, lr
	380	mov r4, #0 /* Fix R4 to 0 */
	381
39e85761	382	#if defined(CONFIG_SYS_MAIN_PWR_ON)
64fdf452 SB	383	ldr r0, =GPIO1_BASE_ADDR
64fdf452 SB	384	ldr r1, [r0, #0x0]
18c63990	385	orr r1, r1, #1 << 23
64fdf452 SB	386	str r1, [r0, #0x0]
64fdf452 SB	387	ldr r1, [r0, #0x4]
18c63990	388	orr r1, r1, #1 << 23
64fdf452	389	str r1, [r0, #0x4]
595f3e56	390	#endif
64fdf452	391
c4fe17f6 FE	392	init_arm_erratum
c4fe17f6 FE	393
64fdf452 SB	394	init_l2cc
	395
	396	init_aips
	397
	398	init_m4if
	399
	400	init_clock
	401
dd227b6e	402	mov pc, r10
74236aca	403	ENDPROC(lowlevel_init)
64fdf452 SB	404
64fdf452 SB	405	/* Board level setting value */
dd227b6e BT	406	#if defined(CONFIG_MX51_PLL_ERRATA)
	407	W_DP_864: .word DP_OP_864
	408	.word DP_MFD_864
	409	.word DP_MFN_864
18c63990	410	W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
dd227b6e BT	411	#else
	412	W_DP_800: .word DP_OP_800
	413	.word DP_MFD_800
	414	.word DP_MFN_800
	415	#endif
	416	#if defined(CONFIG_MX51)
	417	W_DP_665: .word DP_OP_665
	418	.word DP_MFD_665
	419	.word DP_MFN_665
	420	#endif
	421	W_DP_216: .word DP_OP_216
	422	.word DP_MFD_216
	423	.word DP_MFN_216
782b0288 FE	424	W_DP_400: .word DP_OP_400
	425	.word DP_MFD_400
	426	.word DP_MFN_400
	427	W_DP_455: .word DP_OP_455
	428	.word DP_MFD_455
	429	.word DP_MFN_455