[people/ms/u-boot.git] / arch / arm / mach-imx / mx5 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>

#include <linux/errno.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>

#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
#error "CPU_TYPE not defined"
#endif

u32 get_cpu_rev(void)
{
#ifdef CONFIG_MX51
	int system_rev = 0x51000;
#else
	int system_rev = 0x53000;
#endif
	int reg = __raw_readl(ROM_SI_REV);

#if defined(CONFIG_MX51)
	switch (reg) {
	case 0x02:
		system_rev |= CHIP_REV_1_1;
		break;
	case 0x10:
		if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
			system_rev |= CHIP_REV_2_5;
		else
			system_rev |= CHIP_REV_2_0;
		break;
	case 0x20:
		system_rev |= CHIP_REV_3_0;
		break;
	default:
		system_rev |= CHIP_REV_1_0;
		break;
	}
#else
	if (reg < 0x20)
		system_rev |= CHIP_REV_1_0;
	else
		system_rev |= reg;
#endif
	return system_rev;
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	return get_cpu_rev();
}
#endif

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	int i;
	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
	struct fuse_bank *bank = &iim->bank[1];
	struct fuse_bank1_regs *fuse =
			(struct fuse_bank1_regs *)bank->fuse_regs;

	for (i = 0; i < 6; i++)
		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif

#ifdef CONFIG_MX53
void boot_mode_apply(unsigned cfg_val)
{
	writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
}
/*
 * cfg_val will be used for
 * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 *
 * If bit 28 of LPGR is set upon watchdog reset,
 * bits[25:0] of LPGR will move to SBMR.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* usb or serial download */
	{"usb",		MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
	{"sata",	MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
	{"escpi1:0",	MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
	{"escpi1:1",	MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
	{"escpi1:2",	MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
	{"escpi1:3",	MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
	{NULL,		0},
};
#endif
Commit	Line	Data
64fdf452 SB	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
64fdf452 SB	8	*/
	9
	10	#include <common.h>
	11	#include <asm/arch/imx-regs.h>
e4d34492	12	#include <asm/arch/clock.h>
77f11a99 FE	13	#include <asm/arch/sys_proto.h>
77f11a99 FE	14
1221ce45	15	#include <linux/errno.h>
64fdf452	16	#include <asm/io.h>
552a848e	17	#include <asm/mach-imx/boot_mode.h>
64fdf452	18
595f3e56	19	#if !(defined(CONFIG_MX51) \|\| defined(CONFIG_MX53))
ff9f475d JL	20	#error "CPU_TYPE not defined"
	21	#endif
	22
64fdf452 SB	23	u32 get_cpu_rev(void)
64fdf452 SB	24	{
595f3e56 LHR	25	#ifdef CONFIG_MX51
	26	int system_rev = 0x51000;
	27	#else
	28	int system_rev = 0x53000;
	29	#endif
ff9f475d	30	int reg = __raw_readl(ROM_SI_REV);
64fdf452	31
595f3e56	32	#if defined(CONFIG_MX51)
64fdf452 SB	33	switch (reg) {
64fdf452 SB	34	case 0x02:
ff9f475d	35	system_rev \|= CHIP_REV_1_1;
64fdf452 SB	36	break;
	37	case 0x10:
	38	if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
ff9f475d	39	system_rev \|= CHIP_REV_2_5;
64fdf452	40	else
ff9f475d	41	system_rev \|= CHIP_REV_2_0;
64fdf452 SB	42	break;
64fdf452 SB	43	case 0x20:
ff9f475d	44	system_rev \|= CHIP_REV_3_0;
64fdf452	45	break;
64fdf452	46	default:
ff9f475d	47	system_rev \|= CHIP_REV_1_0;
64fdf452 SB	48	break;
64fdf452 SB	49	}
595f3e56	50	#else
aa1cb689	51	if (reg < 0x20)
595f3e56	52	system_rev \|= CHIP_REV_1_0;
aa1cb689 FE	53	else
aa1cb689 FE	54	system_rev \|= reg;
595f3e56	55	#endif
64fdf452 SB	56	return system_rev;
	57	}
	58
11c08d4e FE	59	#ifdef CONFIG_REVISION_TAG
	60	u32 __weak get_board_rev(void)
	61	{
	62	return get_cpu_rev();
	63	}
	64	#endif
	65
78ff1a6c BT	66	#ifndef CONFIG_SYS_DCACHE_OFF
	67	void enable_caches(void)
	68	{
	69	/* Enable D-cache. I-cache is already enabled in start.S */
	70	dcache_enable();
	71	}
	72	#endif
	73
565e39c5	74	#if defined(CONFIG_FEC_MXC)
0d8a7499	75	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
565e39c5 LHR	76	{
	77	int i;
	78	struct iim_regs iim = (struct iim_regs )IMX_IIM_BASE;
	79	struct fuse_bank *bank = &iim->bank[1];
	80	struct fuse_bank1_regs *fuse =
	81	(struct fuse_bank1_regs *)bank->fuse_regs;
	82
	83	for (i = 0; i < 6; i++)
	84	mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
	85	}
	86	#endif
	87
124a06d7 TK	88	#ifdef CONFIG_MX53
	89	void boot_mode_apply(unsigned cfg_val)
	90	{
	91	writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
	92	}
	93	/*
	94	* cfg_val will be used for
	95	* Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
	96	*
	97	* If bit 28 of LPGR is set upon watchdog reset,
	98	* bits[25:0] of LPGR will move to SBMR.
	99	*/
	100	const struct boot_mode soc_boot_modes[] = {
	101	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	102	/* usb or serial download */
	103	{"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
	104	{"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
	105	{"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
	106	{"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
	107	{"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
	108	{"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
	109	/* 4 bit bus width */
	110	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
	111	{"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
	112	{"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
	113	{"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
	114	{NULL, 0},
	115	};
	116	#endif