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Commit | Line | Data |
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23608e23 JL |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
23608e23 JL |
8 | */ |
9 | ||
10 | #include <common.h> | |
1221ce45 | 11 | #include <linux/errno.h> |
23608e23 JL |
12 | #include <asm/io.h> |
13 | #include <asm/arch/imx-regs.h> | |
14 | #include <asm/arch/clock.h> | |
15 | #include <asm/arch/sys_proto.h> | |
552a848e SB |
16 | #include <asm/mach-imx/boot_mode.h> |
17 | #include <asm/mach-imx/dma.h> | |
18 | #include <asm/mach-imx/hab.h> | |
76c91e66 | 19 | #include <stdbool.h> |
5ea7f0e3 PKS |
20 | #include <asm/arch/mxc_hdmi.h> |
21 | #include <asm/arch/crm_regs.h> | |
7a264168 YL |
22 | #include <dm.h> |
23 | #include <imx_thermal.h> | |
1a43dc11 | 24 | #include <mmc.h> |
23608e23 | 25 | |
3d622b78 FE |
26 | enum ldo_reg { |
27 | LDO_ARM, | |
28 | LDO_SOC, | |
29 | LDO_PU, | |
30 | }; | |
31 | ||
20332a06 TK |
32 | struct scu_regs { |
33 | u32 ctrl; | |
34 | u32 config; | |
35 | u32 status; | |
36 | u32 invalidate; | |
37 | u32 fpga_rev; | |
38 | }; | |
39 | ||
1368f993 | 40 | #if defined(CONFIG_IMX_THERMAL) |
7a264168 YL |
41 | static const struct imx_thermal_plat imx6_thermal_plat = { |
42 | .regs = (void *)ANATOP_BASE_ADDR, | |
43 | .fuse_bank = 1, | |
44 | .fuse_word = 6, | |
45 | }; | |
46 | ||
47 | U_BOOT_DEVICE(imx6_thermal) = { | |
48 | .name = "imx_thermal", | |
49 | .platdata = &imx6_thermal_plat, | |
50 | }; | |
51 | #endif | |
52 | ||
6b50bfe5 AA |
53 | #if defined(CONFIG_SECURE_BOOT) |
54 | struct imx_sec_config_fuse_t const imx_sec_config_fuse = { | |
55 | .bank = 0, | |
56 | .word = 6, | |
57 | }; | |
58 | #endif | |
59 | ||
a76df709 GH |
60 | u32 get_nr_cpus(void) |
61 | { | |
62 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; | |
63 | return readl(&scu->config) & 3; | |
64 | } | |
65 | ||
23608e23 JL |
66 | u32 get_cpu_rev(void) |
67 | { | |
a7683867 | 68 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
20332a06 TK |
69 | u32 reg = readl(&anatop->digprog_sololite); |
70 | u32 type = ((reg >> 16) & 0xff); | |
d0acd993 | 71 | u32 major, cfg = 0; |
a7683867 | 72 | |
20332a06 TK |
73 | if (type != MXC_CPU_MX6SL) { |
74 | reg = readl(&anatop->digprog); | |
94db6655 | 75 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; |
d0acd993 | 76 | cfg = readl(&scu->config) & 3; |
20332a06 TK |
77 | type = ((reg >> 16) & 0xff); |
78 | if (type == MXC_CPU_MX6DL) { | |
20332a06 TK |
79 | if (!cfg) |
80 | type = MXC_CPU_MX6SOLO; | |
81 | } | |
94db6655 FE |
82 | |
83 | if (type == MXC_CPU_MX6Q) { | |
84 | if (cfg == 1) | |
85 | type = MXC_CPU_MX6D; | |
86 | } | |
87 | ||
20332a06 | 88 | } |
dfd4861c | 89 | major = ((reg >> 8) & 0xff); |
d0acd993 PF |
90 | if ((major >= 1) && |
91 | ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { | |
92 | major--; | |
93 | type = MXC_CPU_MX6QP; | |
94 | if (cfg == 1) | |
95 | type = MXC_CPU_MX6DP; | |
96 | } | |
20332a06 | 97 | reg &= 0xff; /* mx6 silicon revision */ |
dfd4861c | 98 | return (type << 12) | (reg + (0x10 * (major + 1))); |
23608e23 JL |
99 | } |
100 | ||
9b9449c3 TH |
101 | /* |
102 | * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440) | |
103 | * defines a 2-bit SPEED_GRADING | |
104 | */ | |
105 | #define OCOTP_CFG3_SPEED_SHIFT 16 | |
106 | #define OCOTP_CFG3_SPEED_800MHZ 0 | |
107 | #define OCOTP_CFG3_SPEED_850MHZ 1 | |
108 | #define OCOTP_CFG3_SPEED_1GHZ 2 | |
109 | #define OCOTP_CFG3_SPEED_1P2GHZ 3 | |
110 | ||
d15a244b PF |
111 | /* |
112 | * For i.MX6UL | |
113 | */ | |
114 | #define OCOTP_CFG3_SPEED_528MHZ 1 | |
115 | #define OCOTP_CFG3_SPEED_696MHZ 2 | |
116 | ||
0c7c6fb7 SS |
117 | /* |
118 | * For i.MX6ULL | |
119 | */ | |
120 | #define OCOTP_CFG3_SPEED_792MHZ 2 | |
121 | #define OCOTP_CFG3_SPEED_900MHZ 3 | |
122 | ||
9b9449c3 TH |
123 | u32 get_cpu_speed_grade_hz(void) |
124 | { | |
125 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
126 | struct fuse_bank *bank = &ocotp->bank[0]; | |
127 | struct fuse_bank0_regs *fuse = | |
128 | (struct fuse_bank0_regs *)bank->fuse_regs; | |
129 | uint32_t val; | |
130 | ||
131 | val = readl(&fuse->cfg3); | |
132 | val >>= OCOTP_CFG3_SPEED_SHIFT; | |
133 | val &= 0x3; | |
134 | ||
0c7c6fb7 | 135 | if (is_mx6ul()) { |
d15a244b PF |
136 | if (val == OCOTP_CFG3_SPEED_528MHZ) |
137 | return 528000000; | |
138 | else if (val == OCOTP_CFG3_SPEED_696MHZ) | |
44e67053 | 139 | return 696000000; |
d15a244b PF |
140 | else |
141 | return 0; | |
142 | } | |
143 | ||
0c7c6fb7 SS |
144 | if (is_mx6ull()) { |
145 | if (val == OCOTP_CFG3_SPEED_528MHZ) | |
146 | return 528000000; | |
147 | else if (val == OCOTP_CFG3_SPEED_792MHZ) | |
148 | return 792000000; | |
149 | else if (val == OCOTP_CFG3_SPEED_900MHZ) | |
150 | return 900000000; | |
151 | else | |
152 | return 0; | |
153 | } | |
154 | ||
9b9449c3 TH |
155 | switch (val) { |
156 | /* Valid for IMX6DQ */ | |
157 | case OCOTP_CFG3_SPEED_1P2GHZ: | |
04cb3c0b | 158 | if (is_mx6dq() || is_mx6dqp()) |
9b9449c3 TH |
159 | return 1200000000; |
160 | /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ | |
161 | case OCOTP_CFG3_SPEED_1GHZ: | |
162 | return 996000000; | |
163 | /* Valid for IMX6DQ */ | |
164 | case OCOTP_CFG3_SPEED_850MHZ: | |
04cb3c0b | 165 | if (is_mx6dq() || is_mx6dqp()) |
9b9449c3 TH |
166 | return 852000000; |
167 | /* Valid for IMX6SX/IMX6SDL/IMX6DQ */ | |
168 | case OCOTP_CFG3_SPEED_800MHZ: | |
169 | return 792000000; | |
170 | } | |
171 | return 0; | |
172 | } | |
173 | ||
f0e8e894 TH |
174 | /* |
175 | * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480) | |
176 | * defines a 2-bit Temperature Grade | |
177 | * | |
65496a34 | 178 | * return temperature grade and min/max temperature in Celsius |
f0e8e894 TH |
179 | */ |
180 | #define OCOTP_MEM0_TEMP_SHIFT 6 | |
181 | ||
182 | u32 get_cpu_temp_grade(int *minc, int *maxc) | |
183 | { | |
184 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; | |
185 | struct fuse_bank *bank = &ocotp->bank[1]; | |
186 | struct fuse_bank1_regs *fuse = | |
187 | (struct fuse_bank1_regs *)bank->fuse_regs; | |
188 | uint32_t val; | |
189 | ||
190 | val = readl(&fuse->mem0); | |
191 | val >>= OCOTP_MEM0_TEMP_SHIFT; | |
192 | val &= 0x3; | |
193 | ||
194 | if (minc && maxc) { | |
195 | if (val == TEMP_AUTOMOTIVE) { | |
196 | *minc = -40; | |
197 | *maxc = 125; | |
198 | } else if (val == TEMP_INDUSTRIAL) { | |
199 | *minc = -40; | |
200 | *maxc = 105; | |
201 | } else if (val == TEMP_EXTCOMMERCIAL) { | |
202 | *minc = -20; | |
203 | *maxc = 105; | |
204 | } else { | |
205 | *minc = 0; | |
206 | *maxc = 95; | |
207 | } | |
208 | } | |
209 | return val; | |
210 | } | |
211 | ||
38e70077 FE |
212 | #ifdef CONFIG_REVISION_TAG |
213 | u32 __weak get_board_rev(void) | |
214 | { | |
215 | u32 cpurev = get_cpu_rev(); | |
216 | u32 type = ((cpurev >> 12) & 0xff); | |
217 | if (type == MXC_CPU_MX6SOLO) | |
218 | cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); | |
219 | ||
94db6655 FE |
220 | if (type == MXC_CPU_MX6D) |
221 | cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); | |
222 | ||
38e70077 FE |
223 | return cpurev; |
224 | } | |
225 | #endif | |
226 | ||
e113fd19 FE |
227 | static void clear_ldo_ramp(void) |
228 | { | |
229 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | |
230 | int reg; | |
231 | ||
232 | /* ROM may modify LDO ramp up time according to fuse setting, so in | |
233 | * order to be in the safe side we neeed to reset these settings to | |
234 | * match the reset value: 0'b00 | |
235 | */ | |
236 | reg = readl(&anatop->ana_misc2); | |
237 | reg &= ~(0x3f << 24); | |
238 | writel(reg, &anatop->ana_misc2); | |
239 | } | |
240 | ||
cac833a9 | 241 | /* |
157f45da | 242 | * Set the PMU_REG_CORE register |
cac833a9 | 243 | * |
157f45da | 244 | * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. |
cac833a9 DB |
245 | * Possible values are from 0.725V to 1.450V in steps of |
246 | * 0.025V (25mV). | |
247 | */ | |
3d622b78 | 248 | static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) |
cac833a9 DB |
249 | { |
250 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | |
39f0ac93 | 251 | u32 val, step, old, reg = readl(&anatop->reg_core); |
3d622b78 | 252 | u8 shift; |
cac833a9 | 253 | |
79a57b5a PF |
254 | /* No LDO_SOC/PU/ARM */ |
255 | if (is_mx6sll()) | |
256 | return 0; | |
257 | ||
cac833a9 DB |
258 | if (mv < 725) |
259 | val = 0x00; /* Power gated off */ | |
260 | else if (mv > 1450) | |
261 | val = 0x1F; /* Power FET switched full on. No regulation */ | |
262 | else | |
263 | val = (mv - 700) / 25; | |
264 | ||
e113fd19 FE |
265 | clear_ldo_ramp(); |
266 | ||
3d622b78 FE |
267 | switch (ldo) { |
268 | case LDO_SOC: | |
269 | shift = 18; | |
270 | break; | |
271 | case LDO_PU: | |
272 | shift = 9; | |
273 | break; | |
274 | case LDO_ARM: | |
275 | shift = 0; | |
276 | break; | |
277 | default: | |
278 | return -EINVAL; | |
279 | } | |
280 | ||
39f0ac93 FE |
281 | old = (reg & (0x1F << shift)) >> shift; |
282 | step = abs(val - old); | |
283 | if (step == 0) | |
284 | return 0; | |
285 | ||
3d622b78 | 286 | reg = (reg & ~(0x1F << shift)) | (val << shift); |
cac833a9 | 287 | writel(reg, &anatop->reg_core); |
3d622b78 | 288 | |
39f0ac93 FE |
289 | /* |
290 | * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per | |
291 | * step | |
292 | */ | |
293 | udelay(3 * step); | |
294 | ||
3d622b78 | 295 | return 0; |
cac833a9 DB |
296 | } |
297 | ||
5c92edc2 AH |
298 | static void set_ahb_rate(u32 val) |
299 | { | |
300 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
301 | u32 reg, div; | |
302 | ||
303 | div = get_periph_clk() / val - 1; | |
304 | reg = readl(&mxc_ccm->cbcdr); | |
305 | ||
306 | writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | | |
307 | (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); | |
308 | } | |
309 | ||
16197bb8 AH |
310 | static void clear_mmdc_ch_mask(void) |
311 | { | |
312 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
e1c2d68b PF |
313 | u32 reg; |
314 | reg = readl(&mxc_ccm->ccdr); | |
16197bb8 AH |
315 | |
316 | /* Clear MMDC channel mask */ | |
79a57b5a | 317 | if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll()) |
b777789e YL |
318 | reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); |
319 | else | |
320 | reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); | |
e1c2d68b | 321 | writel(reg, &mxc_ccm->ccdr); |
16197bb8 AH |
322 | } |
323 | ||
97c16dc8 PF |
324 | #define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8 |
325 | ||
1f516faa PF |
326 | static void init_bandgap(void) |
327 | { | |
328 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | |
97c16dc8 PF |
329 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
330 | struct fuse_bank *bank = &ocotp->bank[1]; | |
331 | struct fuse_bank1_regs *fuse = | |
332 | (struct fuse_bank1_regs *)bank->fuse_regs; | |
333 | uint32_t val; | |
334 | ||
1f516faa PF |
335 | /* |
336 | * Ensure the bandgap has stabilized. | |
337 | */ | |
338 | while (!(readl(&anatop->ana_misc0) & 0x80)) | |
339 | ; | |
340 | /* | |
341 | * For best noise performance of the analog blocks using the | |
342 | * outputs of the bandgap, the reftop_selfbiasoff bit should | |
343 | * be set. | |
344 | */ | |
345 | writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); | |
5b66482d | 346 | /* |
97c16dc8 PF |
347 | * On i.MX6ULL,we need to set VBGADJ bits according to the |
348 | * REFTOP_TRIM[3:0] in fuse table | |
349 | * 000 - set REFTOP_VBGADJ[2:0] to 3b'110, | |
350 | * 110 - set REFTOP_VBGADJ[2:0] to 3b'000, | |
351 | * 001 - set REFTOP_VBGADJ[2:0] to 3b'001, | |
352 | * 010 - set REFTOP_VBGADJ[2:0] to 3b'010, | |
353 | * 011 - set REFTOP_VBGADJ[2:0] to 3b'011, | |
354 | * 100 - set REFTOP_VBGADJ[2:0] to 3b'100, | |
355 | * 101 - set REFTOP_VBGADJ[2:0] to 3b'101, | |
356 | * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, | |
5b66482d | 357 | */ |
97c16dc8 PF |
358 | if (is_mx6ull()) { |
359 | val = readl(&fuse->mem0); | |
360 | val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT; | |
361 | val &= 0x7; | |
1f516faa | 362 | |
97c16dc8 PF |
363 | writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, |
364 | &anatop->ana_misc0_set); | |
365 | } | |
366 | } | |
1f516faa | 367 | |
23608e23 JL |
368 | int arch_cpu_init(void) |
369 | { | |
7236297a PF |
370 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
371 | ||
23608e23 JL |
372 | init_aips(); |
373 | ||
16197bb8 AH |
374 | /* Need to clear MMDC_CHx_MASK to make warm reset work. */ |
375 | clear_mmdc_ch_mask(); | |
376 | ||
1f516faa PF |
377 | /* |
378 | * Disable self-bias circuit in the analog bandap. | |
379 | * The self-bias circuit is used by the bandgap during startup. | |
380 | * This bit should be set after the bandgap has initialized. | |
381 | */ | |
382 | init_bandgap(); | |
383 | ||
cdf33c94 | 384 | if (!is_mx6ul() && !is_mx6ull()) { |
e4dc3fc0 PF |
385 | /* |
386 | * When low freq boot is enabled, ROM will not set AHB | |
387 | * freq, so we need to ensure AHB freq is 132MHz in such | |
388 | * scenario. | |
389 | * | |
390 | * To i.MX6UL, when power up, default ARM core and | |
391 | * AHB rate is 396M and 132M. | |
392 | */ | |
393 | if (mxc_get_clock(MXC_ARM_CLK) == 396000000) | |
394 | set_ahb_rate(132000000); | |
395 | } | |
5c92edc2 | 396 | |
f15ece38 PF |
397 | if (is_mx6ul()) { |
398 | if (is_soc_rev(CHIP_REV_1_0) == 0) { | |
399 | /* | |
400 | * According to the design team's requirement on | |
401 | * i.MX6UL,the PMIC_STBY_REQ PAD should be configured | |
402 | * as open drain 100K (0x0000b8a0). | |
403 | * Only exists on TO1.0 | |
404 | */ | |
405 | writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); | |
406 | } else { | |
407 | /* | |
408 | * From TO1.1, SNVS adds internal pull up control | |
409 | * for POR_B, the register filed is GPBIT[1:0], | |
410 | * after system boot up, it can be set to 2b'01 | |
411 | * to disable internal pull up.It can save about | |
412 | * 30uA power in SNVS mode. | |
413 | */ | |
414 | writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & | |
415 | (~0x1400)) | 0x400, | |
416 | MX6UL_SNVS_LP_BASE_ADDR + 0x10); | |
417 | } | |
7082d879 PF |
418 | } |
419 | ||
b4714616 PF |
420 | if (is_mx6ull()) { |
421 | /* | |
422 | * GPBIT[1:0] is suggested to set to 2'b11: | |
423 | * 2'b00 : always PUP100K | |
424 | * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL | |
425 | * 2'b10 : always disable PUP100K | |
426 | * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL | |
427 | * register offset is different from i.MX6UL, since | |
428 | * i.MX6UL is fixed by ECO. | |
429 | */ | |
430 | writel(readl(MX6UL_SNVS_LP_BASE_ADDR) | | |
431 | 0x3, MX6UL_SNVS_LP_BASE_ADDR); | |
432 | } | |
433 | ||
7082d879 | 434 | /* Set perclk to source from OSC 24MHz */ |
9402cafb PF |
435 | if (is_mx6sl()) |
436 | setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); | |
0f8ec145 | 437 | |
76c91e66 | 438 | imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ |
ae695b18 | 439 | |
7236297a PF |
440 | if (is_mx6sx()) |
441 | setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); | |
442 | ||
9d16c52f DB |
443 | init_src(); |
444 | ||
23608e23 JL |
445 | return 0; |
446 | } | |
23608e23 | 447 | |
216d286c PF |
448 | #ifdef CONFIG_ENV_IS_IN_MMC |
449 | __weak int board_mmc_get_env_dev(int devno) | |
450 | { | |
451 | return CONFIG_SYS_MMC_ENV_DEV; | |
452 | } | |
453 | ||
1a43dc11 | 454 | static int mmc_get_boot_dev(void) |
216d286c PF |
455 | { |
456 | struct src *src_regs = (struct src *)SRC_BASE_ADDR; | |
457 | u32 soc_sbmr = readl(&src_regs->sbmr1); | |
458 | u32 bootsel; | |
459 | int devno; | |
460 | ||
461 | /* | |
462 | * Refer to | |
463 | * "i.MX 6Dual/6Quad Applications Processor Reference Manual" | |
464 | * Chapter "8.5.3.1 Expansion Device eFUSE Configuration" | |
465 | * i.MX6SL/SX/UL has same layout. | |
466 | */ | |
467 | bootsel = (soc_sbmr & 0x000000FF) >> 6; | |
468 | ||
1a43dc11 | 469 | /* No boot from sd/mmc */ |
216d286c | 470 | if (bootsel != 1) |
1a43dc11 | 471 | return -1; |
216d286c PF |
472 | |
473 | /* BOOT_CFG2[3] and BOOT_CFG2[4] */ | |
474 | devno = (soc_sbmr & 0x00001800) >> 11; | |
475 | ||
1a43dc11 SM |
476 | return devno; |
477 | } | |
478 | ||
479 | int mmc_get_env_dev(void) | |
480 | { | |
481 | int devno = mmc_get_boot_dev(); | |
482 | ||
483 | /* If not boot from sd/mmc, use default value */ | |
484 | if (devno < 0) | |
485 | return CONFIG_SYS_MMC_ENV_DEV; | |
486 | ||
216d286c PF |
487 | return board_mmc_get_env_dev(devno); |
488 | } | |
1a43dc11 SM |
489 | |
490 | #ifdef CONFIG_SYS_MMC_ENV_PART | |
491 | __weak int board_mmc_get_env_part(int devno) | |
492 | { | |
493 | return CONFIG_SYS_MMC_ENV_PART; | |
494 | } | |
495 | ||
496 | uint mmc_get_env_part(struct mmc *mmc) | |
497 | { | |
498 | int devno = mmc_get_boot_dev(); | |
499 | ||
500 | /* If not boot from sd/mmc, use default value */ | |
501 | if (devno < 0) | |
502 | return CONFIG_SYS_MMC_ENV_PART; | |
503 | ||
504 | return board_mmc_get_env_part(devno); | |
505 | } | |
506 | #endif | |
216d286c PF |
507 | #endif |
508 | ||
39f0ac93 FE |
509 | int board_postclk_init(void) |
510 | { | |
79a57b5a PF |
511 | /* NO LDO SOC on i.MX6SLL */ |
512 | if (is_mx6sll()) | |
513 | return 0; | |
514 | ||
39f0ac93 FE |
515 | set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
23608e23 | 520 | #if defined(CONFIG_FEC_MXC) |
be252b65 | 521 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) |
23608e23 | 522 | { |
8f3ff11c BT |
523 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
524 | struct fuse_bank *bank = &ocotp->bank[4]; | |
23608e23 JL |
525 | struct fuse_bank4_regs *fuse = |
526 | (struct fuse_bank4_regs *)bank->fuse_regs; | |
527 | ||
6615da4d | 528 | if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) { |
d4d1dd67 YL |
529 | u32 value = readl(&fuse->mac_addr2); |
530 | mac[0] = value >> 24 ; | |
531 | mac[1] = value >> 16 ; | |
532 | mac[2] = value >> 8 ; | |
533 | mac[3] = value ; | |
534 | ||
535 | value = readl(&fuse->mac_addr1); | |
536 | mac[4] = value >> 24 ; | |
537 | mac[5] = value >> 16 ; | |
538 | ||
539 | } else { | |
540 | u32 value = readl(&fuse->mac_addr1); | |
541 | mac[0] = (value >> 8); | |
542 | mac[1] = value ; | |
543 | ||
544 | value = readl(&fuse->mac_addr0); | |
545 | mac[2] = value >> 24 ; | |
546 | mac[3] = value >> 16 ; | |
547 | mac[4] = value >> 8 ; | |
548 | mac[5] = value ; | |
549 | } | |
23608e23 JL |
550 | |
551 | } | |
552 | #endif | |
124a06d7 | 553 | |
124a06d7 TK |
554 | /* |
555 | * cfg_val will be used for | |
556 | * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] | |
f2863ff3 NK |
557 | * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] |
558 | * instead of SBMR1 to determine the boot device. | |
124a06d7 TK |
559 | */ |
560 | const struct boot_mode soc_boot_modes[] = { | |
561 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, | |
562 | /* reserved value should start rom usb */ | |
3fd95790 SA |
563 | #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) |
564 | {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, | |
565 | #else | |
81c4eccb | 566 | {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, |
3fd95790 | 567 | #endif |
124a06d7 | 568 | {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, |
2d59e3ec ND |
569 | {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, |
570 | {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, | |
571 | {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, | |
572 | {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, | |
124a06d7 TK |
573 | /* 4 bit bus width */ |
574 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, | |
575 | {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
576 | {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
577 | {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, | |
578 | {NULL, 0}, | |
579 | }; | |
8f393776 | 580 | |
eb111bb3 PF |
581 | void reset_misc(void) |
582 | { | |
583 | #ifdef CONFIG_VIDEO_MXS | |
584 | lcdif_power_down(); | |
585 | #endif | |
586 | } | |
587 | ||
8f393776 SW |
588 | void s_init(void) |
589 | { | |
8467faef | 590 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
9293d7fd | 591 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
8467faef EN |
592 | u32 mask480; |
593 | u32 mask528; | |
9293d7fd | 594 | u32 reg, periph1, periph2; |
a3df99b5 | 595 | |
79a57b5a | 596 | if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll()) |
a3df99b5 FE |
597 | return; |
598 | ||
8467faef EN |
599 | /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs |
600 | * to make sure PFD is working right, otherwise, PFDs may | |
601 | * not output clock after reset, MX6DL and MX6SL have added 396M pfd | |
602 | * workaround in ROM code, as bus clock need it | |
603 | */ | |
604 | ||
605 | mask480 = ANATOP_PFD_CLKGATE_MASK(0) | | |
606 | ANATOP_PFD_CLKGATE_MASK(1) | | |
607 | ANATOP_PFD_CLKGATE_MASK(2) | | |
608 | ANATOP_PFD_CLKGATE_MASK(3); | |
9293d7fd | 609 | mask528 = ANATOP_PFD_CLKGATE_MASK(1) | |
8467faef EN |
610 | ANATOP_PFD_CLKGATE_MASK(3); |
611 | ||
9293d7fd YL |
612 | reg = readl(&ccm->cbcmr); |
613 | periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) | |
614 | >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); | |
615 | periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) | |
616 | >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); | |
617 | ||
618 | /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ | |
619 | if ((periph2 != 0x2) && (periph1 != 0x2)) | |
620 | mask528 |= ANATOP_PFD_CLKGATE_MASK(0); | |
621 | ||
622 | if ((periph2 != 0x1) && (periph1 != 0x1) && | |
623 | (periph2 != 0x3) && (periph1 != 0x3)) | |
8467faef | 624 | mask528 |= ANATOP_PFD_CLKGATE_MASK(2); |
9293d7fd | 625 | |
8467faef EN |
626 | writel(mask480, &anatop->pfd_480_set); |
627 | writel(mask528, &anatop->pfd_528_set); | |
628 | writel(mask480, &anatop->pfd_480_clr); | |
629 | writel(mask528, &anatop->pfd_528_clr); | |
8f393776 | 630 | } |
5ea7f0e3 PKS |
631 | |
632 | #ifdef CONFIG_IMX_HDMI | |
633 | void imx_enable_hdmi_phy(void) | |
634 | { | |
635 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; | |
636 | u8 reg; | |
637 | reg = readb(&hdmi->phy_conf0); | |
638 | reg |= HDMI_PHY_CONF0_PDZ_MASK; | |
639 | writeb(reg, &hdmi->phy_conf0); | |
640 | udelay(3000); | |
641 | reg |= HDMI_PHY_CONF0_ENTMDS_MASK; | |
642 | writeb(reg, &hdmi->phy_conf0); | |
643 | udelay(3000); | |
644 | reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; | |
645 | writeb(reg, &hdmi->phy_conf0); | |
646 | writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); | |
647 | } | |
648 | ||
649 | void imx_setup_hdmi(void) | |
650 | { | |
651 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
652 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; | |
00b1d2d3 PF |
653 | int reg, count; |
654 | u8 val; | |
5ea7f0e3 PKS |
655 | |
656 | /* Turn on HDMI PHY clock */ | |
657 | reg = readl(&mxc_ccm->CCGR2); | |
658 | reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| | |
659 | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; | |
660 | writel(reg, &mxc_ccm->CCGR2); | |
661 | writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); | |
662 | reg = readl(&mxc_ccm->chsccdr); | |
663 | reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| | |
664 | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| | |
665 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); | |
666 | reg |= (CHSCCDR_PODF_DIVIDE_BY_3 | |
667 | << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | |
668 | |(CHSCCDR_IPU_PRE_CLK_540M_PFD | |
669 | << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); | |
670 | writel(reg, &mxc_ccm->chsccdr); | |
00b1d2d3 PF |
671 | |
672 | /* Clear the overflow condition */ | |
673 | if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { | |
674 | /* TMDS software reset */ | |
675 | writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); | |
676 | val = readb(&hdmi->fc_invidconf); | |
677 | /* Need minimum 3 times to write to clear the register */ | |
678 | for (count = 0 ; count < 5 ; count++) | |
679 | writeb(val, &hdmi->fc_invidconf); | |
680 | } | |
5ea7f0e3 PKS |
681 | } |
682 | #endif | |
0623d375 PF |
683 | |
684 | #ifdef CONFIG_IMX_BOOTAUX | |
685 | int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) | |
686 | { | |
687 | struct src *src_reg; | |
688 | u32 stack, pc; | |
689 | ||
690 | if (!boot_private_data) | |
691 | return -EINVAL; | |
692 | ||
693 | stack = *(u32 *)boot_private_data; | |
694 | pc = *(u32 *)(boot_private_data + 4); | |
695 | ||
696 | /* Set the stack and pc to M4 bootROM */ | |
697 | writel(stack, M4_BOOTROM_BASE_ADDR); | |
698 | writel(pc, M4_BOOTROM_BASE_ADDR + 4); | |
699 | ||
700 | /* Enable M4 */ | |
701 | src_reg = (struct src *)SRC_BASE_ADDR; | |
702 | clrsetbits_le32(&src_reg->scr, SRC_SCR_M4C_NON_SCLR_RST_MASK, | |
703 | SRC_SCR_M4_ENABLE_MASK); | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | int arch_auxiliary_core_check_up(u32 core_id) | |
709 | { | |
710 | struct src *src_reg = (struct src *)SRC_BASE_ADDR; | |
711 | unsigned val; | |
712 | ||
713 | val = readl(&src_reg->scr); | |
714 | ||
715 | if (val & SRC_SCR_M4C_NON_SCLR_RST_MASK) | |
716 | return 0; /* assert in reset */ | |
717 | ||
718 | return 1; | |
719 | } | |
720 | #endif |