[people/ms/u-boot.git] / arch / arm / mach-keystone / init.c

/*
 * Keystone2: Architecture initialization
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/psc_defs.h>

#define MAX_PCI_PORTS		2
enum pci_mode	{
	ENDPOINT,
	LEGACY_ENDPOINT,
	ROOTCOMPLEX,
};

#define DEVCFG_MODE_MASK		(BIT(2) | BIT(1))
#define DEVCFG_MODE_SHIFT		1

void chip_configuration_unlock(void)
{
	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}

#ifdef CONFIG_SOC_K2L
void osr_init(void)
{
	u32 i;
	u32 j;
	u32 val;
	u32 base = KS2_OSR_CFG_BASE;
	u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];

	/* Enable the OSR clock domain */
	psc_enable_module(KS2_LPSC_OSR);

	/* Disable OSR ECC check for all the ram banks */
	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
		val = i | KS2_OSR_ECC_VEC_TRIG_RD |
			(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);

		writel(val , base + KS2_OSR_ECC_VEC);

		/**
		 * wait till read is done.
		 * Print should be added after earlyprintk support is added.
		 */
		for (j = 0; j < 10000; j++) {
			val = readl(base + KS2_OSR_ECC_VEC);
			if (val & KS2_OSR_ECC_VEC_RD_DONE)
				break;
		}

		ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
						KS2_OSR_ECC_CTRL_CHK;

		writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
		writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
	}

	/* Reset OSR memory to all zeros */
	for (i = 0; i < KS2_OSR_SIZE; i += 4)
		writel(0, KS2_OSR_DATA_BASE + i);

	/* Enable OSR ECC check for all the ram banks */
	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
		writel(ecc_ctrl[i] |
		       KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
}
#endif

/* Function to set up PCIe mode */
static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
{
	u32 val = __raw_readl(KS2_DEVCFG);

	if (pcie_port >= MAX_PCI_PORTS)
		return;

	/**
	 * each pci port has two bits for mode and it starts at
	 * bit 1. So use port number to get the right bit position.
	 */
	pcie_port <<= 1;
	val &= ~(DEVCFG_MODE_MASK << pcie_port);
	val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
	__raw_writel(val, KS2_DEVCFG);
}

static void msmc_k2hkle_common_setup(void)
{
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
#ifdef KS2_MSMC_SEGMENT_QM_PDSP
	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
#endif
	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
}

static void msmc_k2hk_setup(void)
{
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
}

static inline void msmc_k2l_setup(void)
{
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
	msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
}

static inline void msmc_k2e_setup(void)
{
	msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
	msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
}

static void msmc_k2g_setup(void)
{
	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
	msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
}

int arch_cpu_init(void)
{
	chip_configuration_unlock();
	icache_enable();

	if (cpu_is_k2g()) {
		msmc_k2g_setup();
	} else {
		msmc_k2hkle_common_setup();
		if (cpu_is_k2e())
			msmc_k2e_setup();
		else if (cpu_is_k2l())
			msmc_k2l_setup();
		else
			msmc_k2hk_setup();
	}

	/* Initialize the PCIe-0 to work as Root Complex */
	config_pcie_mode(0, ROOTCOMPLEX);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
	/* Initialize the PCIe-1 to work as Root Complex */
	config_pcie_mode(1, ROOTCOMPLEX);
#endif
#ifdef CONFIG_SOC_K2L
	osr_init();
#endif

	/*
	 * just initialise the COM2 port so that TI specific
	 * UART register PWREMU_MGMT is initialized. Linux UART
	 * driver doesn't handle this.
	 */
#ifndef CONFIG_DM_SERIAL
	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
#endif

	return 0;
}

void reset_cpu(ulong addr)
{
	volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
	u32 tmp;

	tmp = *rstctrl & KS2_RSTCTRL_MASK;
	*rstctrl = tmp | KS2_RSTCTRL_KEY;

	*rstctrl &= KS2_RSTCTRL_SWRST;

	for (;;)
		;
}

void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
#endif
}

#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
	u16 cpu = get_part_number();
	u8 rev = cpu_revision();

	puts("CPU: ");
	switch (cpu) {
	case CPU_66AK2Hx:
		puts("66AK2Hx SR");
		break;
	case CPU_66AK2Lx:
		puts("66AK2Lx SR");
		break;
	case CPU_66AK2Ex:
		puts("66AK2Ex SR");
		break;
	case CPU_66AK2Gx:
		puts("66AK2Gx SR");
		break;
	default:
		puts("Unknown\n");
	}

	if (rev == 2)
		puts("2.0\n");
	else if (rev == 1)
		puts("1.1\n");
	else if (rev == 0)
		puts("1.0\n");

	return 0;
}
#endif
Commit	Line	Data
ef509b90 VA	1	/*
	2	* Keystone2: Architecture initialization
	3	*
	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
afee59cd	11	#include <ns16550.h>
ef509b90	12	#include <asm/io.h>
20187fd1	13	#include <asm/arch/msmc.h>
ef509b90 VA	14	#include <asm/arch/clock.h>
ef509b90 VA	15	#include <asm/arch/hardware.h>
b66604fb	16	#include <asm/arch/psc_defs.h>
ef509b90	17
58927a96 KM	18	#define MAX_PCI_PORTS 2
	19	enum pci_mode {
	20	ENDPOINT,
	21	LEGACY_ENDPOINT,
	22	ROOTCOMPLEX,
	23	};
	24
	25	#define DEVCFG_MODE_MASK (BIT(2) \| BIT(1))
	26	#define DEVCFG_MODE_SHIFT 1
	27
ef509b90 VA	28	void chip_configuration_unlock(void)
ef509b90 VA	29	{
3d315386 KI	30	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
3d315386 KI	31	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
ef509b90 VA	32	}
ef509b90 VA	33
b66604fb HZ	34	#ifdef CONFIG_SOC_K2L
	35	void osr_init(void)
	36	{
	37	u32 i;
	38	u32 j;
	39	u32 val;
	40	u32 base = KS2_OSR_CFG_BASE;
	41	u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
	42
	43	/* Enable the OSR clock domain */
	44	psc_enable_module(KS2_LPSC_OSR);
	45
	46	/* Disable OSR ECC check for all the ram banks */
	47	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
	48	val = i \| KS2_OSR_ECC_VEC_TRIG_RD \|
	49	(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
	50
	51	writel(val , base + KS2_OSR_ECC_VEC);
	52
	53	/**
	54	* wait till read is done.
	55	* Print should be added after earlyprintk support is added.
	56	*/
	57	for (j = 0; j < 10000; j++) {
	58	val = readl(base + KS2_OSR_ECC_VEC);
	59	if (val & KS2_OSR_ECC_VEC_RD_DONE)
	60	break;
	61	}
	62
	63	ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
	64	KS2_OSR_ECC_CTRL_CHK;
	65
	66	writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
	67	writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
	68	}
	69
	70	/* Reset OSR memory to all zeros */
	71	for (i = 0; i < KS2_OSR_SIZE; i += 4)
	72	writel(0, KS2_OSR_DATA_BASE + i);
	73
	74	/* Enable OSR ECC check for all the ram banks */
	75	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
	76	writel(ecc_ctrl[i] \|
	77	KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
	78	}
	79	#endif
	80
58927a96 KM	81	/* Function to set up PCIe mode */
	82	static void config_pcie_mode(int pcie_port, enum pci_mode mode)
	83	{
	84	u32 val = __raw_readl(KS2_DEVCFG);
	85
	86	if (pcie_port >= MAX_PCI_PORTS)
	87	return;
	88
	89	/**
	90	* each pci port has two bits for mode and it starts at
	91	* bit 1. So use port number to get the right bit position.
	92	*/
	93	pcie_port <<= 1;
	94	val &= ~(DEVCFG_MODE_MASK << pcie_port);
	95	val \|= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
	96	__raw_writel(val, KS2_DEVCFG);
	97	}
	98
1f807a9f NM	99	static void msmc_k2hkle_common_setup(void)
1f807a9f NM	100	{
2283284b	101	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
1f807a9f NM	102	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
	103	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
	104	#ifdef KS2_MSMC_SEGMENT_QM_PDSP
	105	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
	106	#endif
	107	msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
2283284b NM	108	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
	109	}
	110
	111	static void msmc_k2hk_setup(void)
	112	{
	113	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
	114	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
	115	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
	116	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
	117	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
	118	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
	119	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
	120	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
1f807a9f NM	121	}
	122
	123	static inline void msmc_k2l_setup(void)
	124	{
2283284b NM	125	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
	126	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
	127	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
1f807a9f NM	128	msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
	129	}
	130
	131	static inline void msmc_k2e_setup(void)
	132	{
	133	msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
2283284b NM	134	msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
2283284b NM	135	msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
1f807a9f NM	136	}
1f807a9f NM	137
2283284b	138	static void msmc_k2g_setup(void)
1f807a9f	139	{
2283284b	140	msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
1f807a9f	141	msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
2283284b NM	142	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
2283284b NM	143	msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
1f807a9f NM	144	msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
1f807a9f NM	145	msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
2283284b NM	146	msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
	147	msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
	148	msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
	149	msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
	150	msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
	151	msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
1f807a9f NM	152	}
1f807a9f NM	153
ef509b90 VA	154	int arch_cpu_init(void)
	155	{
	156	chip_configuration_unlock();
	157	icache_enable();
	158
1f807a9f NM	159	if (cpu_is_k2g()) {
	160	msmc_k2g_setup();
	161	} else {
	162	msmc_k2hkle_common_setup();
	163	if (cpu_is_k2e())
	164	msmc_k2e_setup();
	165	else if (cpu_is_k2l())
	166	msmc_k2l_setup();
2283284b NM	167	else
2283284b NM	168	msmc_k2hk_setup();
1f807a9f	169	}
58927a96 KM	170
	171	/* Initialize the PCIe-0 to work as Root Complex */
	172	config_pcie_mode(0, ROOTCOMPLEX);
bc45d572	173	#if defined(CONFIG_SOC_K2E) \|\| defined(CONFIG_SOC_K2L)
58927a96 KM	174	/* Initialize the PCIe-1 to work as Root Complex */
58927a96 KM	175	config_pcie_mode(1, ROOTCOMPLEX);
ef509b90	176	#endif
b66604fb HZ	177	#ifdef CONFIG_SOC_K2L
	178	osr_init();
	179	#endif
ef509b90	180
afee59cd MK	181	/*
	182	* just initialise the COM2 port so that TI specific
	183	* UART register PWREMU_MGMT is initialized. Linux UART
	184	* driver doesn't handle this.
	185	*/
8c80b193	186	#ifndef CONFIG_DM_SERIAL
afee59cd MK	187	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
afee59cd MK	188	CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
8c80b193	189	#endif
afee59cd	190
ef509b90 VA	191	return 0;
	192	}
	193
	194	void reset_cpu(ulong addr)
	195	{
	196	volatile u32 rstctrl = (volatile u32 )(KS2_RSTCTRL);
	197	u32 tmp;
	198
	199	tmp = *rstctrl & KS2_RSTCTRL_MASK;
	200	*rstctrl = tmp \| KS2_RSTCTRL_KEY;
	201
	202	*rstctrl &= KS2_RSTCTRL_SWRST;
	203
	204	for (;;)
	205	;
	206	}
	207
	208	void enable_caches(void)
	209	{
	210	#ifndef CONFIG_SYS_DCACHE_OFF
	211	/* Enable D-cache. I-cache is already enabled in start.S */
	212	dcache_enable();
	213	#endif
	214	}
aeabe652 LV	215
	216	#if defined(CONFIG_DISPLAY_CPUINFO)
	217	int print_cpuinfo(void)
	218	{
	219	u16 cpu = get_part_number();
	220	u8 rev = cpu_revision();
	221
	222	puts("CPU: ");
	223	switch (cpu) {
	224	case CPU_66AK2Hx:
	225	puts("66AK2Hx SR");
	226	break;
	227	case CPU_66AK2Lx:
	228	puts("66AK2Lx SR");
	229	break;
	230	case CPU_66AK2Ex:
	231	puts("66AK2Ex SR");
	232	break;
f11a328b LV	233	case CPU_66AK2Gx:
	234	puts("66AK2Gx SR");
	235	break;
aeabe652 LV	236	default:
	237	puts("Unknown\n");
	238	}
	239
	240	if (rev == 2)
	241	puts("2.0\n");
	242	else if (rev == 1)
	243	puts("1.1\n");
	244	else if (rev == 0)
	245	puts("1.0\n");
	246
	247	return 0;
	248	}
	249	#endif