[people/ms/u-boot.git] / arch / arm / mach-meson / board.c

/*
 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <libfdt.h>
#include <linux/err.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
#include <asm/armv8/mmu.h>
#include <asm/unaligned.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	const fdt64_t *val;
	int offset;
	int len;

	offset = fdt_path_offset(gd->fdt_blob, "/memory");
	if (offset < 0)
		return -EINVAL;

	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
	if (len < sizeof(*val) * 2)
		return -EINVAL;

	/* Use unaligned access since cache is still disabled */
	gd->ram_size = get_unaligned_be64(&val[1]);

	return 0;
}

int dram_init_banksize(void)
{
	/* Reserve first 16 MiB of RAM for firmware */
	gd->bd->bi_dram[0].start = 0x1000000;
	gd->bd->bi_dram[0].size  = 0xf000000;
	/* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
	gd->bd->bi_dram[1].start = 0x10000000;
	gd->bd->bi_dram[1].size  = gd->ram_size - 0x10200000;
	return 0;
}

void reset_cpu(ulong addr)
{
	psci_system_reset();
}

static struct mm_region gxbb_mem_map[] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		.virt = 0x80000000UL,
		.phys = 0x80000000UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		/* List terminator */
		0,
	}
};

struct mm_region *mem_map = gxbb_mem_map;
Commit	Line	Data
bfcef28a BG	1	/*
	2	* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <libfdt.h>
	9	#include <linux/err.h>
	10	#include <asm/arch/gxbb.h>
c7757d46	11	#include <asm/arch/sm.h>
bfcef28a BG	12	#include <asm/armv8/mmu.h>
	13	#include <asm/unaligned.h>
	14
	15	DECLARE_GLOBAL_DATA_PTR;
	16
	17	int dram_init(void)
	18	{
	19	const fdt64_t *val;
	20	int offset;
	21	int len;
	22
	23	offset = fdt_path_offset(gd->fdt_blob, "/memory");
	24	if (offset < 0)
	25	return -EINVAL;
	26
	27	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
	28	if (len < sizeof(val) 2)
	29	return -EINVAL;
	30
	31	/* Use unaligned access since cache is still disabled */
	32	gd->ram_size = get_unaligned_be64(&val[1]);
	33
	34	return 0;
	35	}
	36
76b00aca	37	int dram_init_banksize(void)
bfcef28a BG	38	{
bfcef28a BG	39	/* Reserve first 16 MiB of RAM for firmware */
e42f096f	40	gd->bd->bi_dram[0].start = 0x1000000;
	41	gd->bd->bi_dram[0].size = 0xf000000;
	42	/* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
	43	gd->bd->bi_dram[1].start = 0x10000000;
	44	gd->bd->bi_dram[1].size = gd->ram_size - 0x10200000;
76b00aca	45	return 0;
bfcef28a BG	46	}
	47
	48	void reset_cpu(ulong addr)
	49	{
51bfb5b6	50	psci_system_reset();
bfcef28a BG	51	}
	52
	53	static struct mm_region gxbb_mem_map[] = {
	54	{
cd4b0c5f YS	55	.virt = 0x0UL,
cd4b0c5f YS	56	.phys = 0x0UL,
bfcef28a BG	57	.size = 0x80000000UL,
	58	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	59	PTE_BLOCK_INNER_SHARE
	60	}, {
cd4b0c5f YS	61	.virt = 0x80000000UL,
cd4b0c5f YS	62	.phys = 0x80000000UL,
bfcef28a BG	63	.size = 0x80000000UL,
	64	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	65	PTE_BLOCK_NON_SHARE \|
	66	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	67	}, {
	68	/* List terminator */
	69	0,
	70	}
	71	};
	72
	73	struct mm_region *mem_map = gxbb_mem_map;