projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 41e5ee54 SR |
1 | /* |
| 2 | * (C) Copyright 2011 | |
| 3 | * Marvell Semiconductor <www.marvell.com> | |
| 4 | * Written-by: Lei Wen <leiwen@marvell.com> | |
| 5 | * | |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | |
| 7 | */ | |
| 8 | ||
| 9 | /* | |
| 10 | * This file should be included in board config header file. | |
| 11 | * | |
| f7c0ef07 | 12 | * It supports common definitions for MVEBU platforms |
| 41e5ee54 SR |
13 | */ |
| 14 | ||
| 250eea74 SR |
15 | #ifndef _MVEBU_CONFIG_H |
| 16 | #define _MVEBU_CONFIG_H | |
| 41e5ee54 SR |
17 | |
| 18 | #include <asm/arch/soc.h> | |
| 19 | ||
| 81e33f4b SR |
20 | #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_38X) |
| 21 | /* | |
| 22 | * Set this for the common xor register definitions needed in dram.c | |
| 23 | * for A38x as well here. | |
| 24 | */ | |
| 41e5ee54 | 25 | #define MV88F78X60 /* for the DDR training bin_hdr code */ |
| f7c0ef07 | 26 | #endif |
| 41e5ee54 SR |
27 | |
| 28 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
| 29 | ||
| 8a02ec1d SR |
30 | #define CONFIG_SYS_L2_PL310 |
| 31 | ||
| 32 | #ifdef CONFIG_SPL_BUILD | |
| 33 | #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ | |
| 34 | #endif | |
| 35 | ||
| 41e5ee54 SR |
36 | /* |
| 37 | * By default kwbimage.cfg from board specific folder is used | |
| 38 | * If for some board, different configuration file need to be used, | |
| 39 | * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file | |
| 40 | */ | |
| 41 | #ifndef CONFIG_SYS_KWD_CONFIG | |
| 42 | #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg | |
| 43 | #endif /* CONFIG_SYS_KWD_CONFIG */ | |
| 44 | ||
| 45 | /* Add target to build it automatically upon "make" */ | |
| 1e0b5984 SR |
46 | #ifdef CONFIG_SPL |
| 47 | #define CONFIG_BUILD_TARGET "u-boot-spl.kwb" | |
| 1e0b5984 | 48 | #endif |
| 41e5ee54 SR |
49 | |
| 50 | /* end of 16M scrubbed by training in bootrom */ | |
| 51 | #define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 | |
| 52 | #define CONFIG_NR_DRAM_BANKS_MAX 2 | |
| 53 | ||
| 54 | #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE | |
| 55 | ||
| 56 | /* | |
| 57 | * SPI Flash configuration | |
| 58 | */ | |
| 59 | #ifdef CONFIG_CMD_SF | |
| 09a54c00 | 60 | #define CONFIG_KIRKWOOD_SPI |
| 41e5ee54 SR |
61 | #ifndef CONFIG_ENV_SPI_BUS |
| 62 | # define CONFIG_ENV_SPI_BUS 0 | |
| 63 | #endif | |
| 64 | #ifndef CONFIG_ENV_SPI_CS | |
| 65 | # define CONFIG_ENV_SPI_CS 0 | |
| 66 | #endif | |
| 67 | #ifndef CONFIG_ENV_SPI_MAX_HZ | |
| 68 | # define CONFIG_ENV_SPI_MAX_HZ 50000000 | |
| 69 | #endif | |
| 70 | #endif | |
| 71 | ||
| 09a54c00 SR |
72 | /* Needed for SPI NOR booting in SPL */ |
| 73 | #define CONFIG_DM_SEQ_ALIAS 1 | |
| 74 | ||
| 41e5ee54 SR |
75 | /* |
| 76 | * Ethernet Driver configuration | |
| 77 | */ | |
| 78 | #ifdef CONFIG_CMD_NET | |
| 79 | #define CONFIG_CMD_MII | |
| 80 | #define CONFIG_MII /* expose smi ove miiphy interface */ | |
| 81 | #define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ | |
| 82 | #define CONFIG_PHYLIB | |
| 83 | #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ | |
| 84 | #define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ | |
| 9eb14cc4 SR |
85 | #define CONFIG_ARP_TIMEOUT 200 |
| 86 | #define CONFIG_NET_RETRY_COUNT 50 | |
| 41e5ee54 SR |
87 | #endif /* CONFIG_CMD_NET */ |
| 88 | ||
| 89 | /* | |
| 90 | * I2C related stuff | |
| 91 | */ | |
| 92 | #ifdef CONFIG_CMD_I2C | |
| 93 | #ifndef CONFIG_SYS_I2C_SOFT | |
| 94 | #define CONFIG_I2C_MVTWSI | |
| 95 | #endif | |
| 96 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
| 97 | #define CONFIG_SYS_I2C_SPEED 100000 | |
| 98 | #endif | |
| 99 | ||
| 2fbc18fe SR |
100 | /* Use common timer */ |
| 101 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | |
| 102 | #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) | |
| 103 | #define CONFIG_SYS_TIMER_RATE 25000000 | |
| 104 | ||
| 250eea74 | 105 | #endif /* __MVEBU_CONFIG_H */ |