[people/ms/u-boot.git] / arch / arm / mach-orion5x / dram.c

/*
 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
 *
 * Based on original Kirkwood support which is
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <config.h>
#include <asm/arch/cpu.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * orion5x_sdram_bar - reads SDRAM Base Address Register
 */
u32 orion5x_sdram_bar(enum memory_bank bank)
{
	struct orion5x_ddr_addr_decode_registers *winregs =
		(struct orion5x_ddr_addr_decode_registers *)
		ORION5X_DRAM_BASE;

	u32 result = 0;
	u32 enable = 0x01 & winregs[bank].size;

	if ((!enable) || (bank > BANK3))
		return 0;

	result = winregs[bank].base;
	return result;
}
int dram_init (void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size(
			(long *) orion5x_sdram_bar(0),
			CONFIG_MAX_RAM_BANK_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	int i;

	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
		gd->bd->bi_dram[i].size = get_ram_size(
			(long *) (gd->bd->bi_dram[i].start),
			CONFIG_MAX_RAM_BANK_SIZE);
	}

	return 0;
}
Commit	Line	Data
0c61e6f9	1	/*
57b4bce9	2	* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
0c61e6f9 AA	3	*
	4	* Based on original Kirkwood support which is
	5	* (C) Copyright 2009
	6	* Marvell Semiconductor <www.marvell.com>
	7	* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
0c61e6f9 AA	10	*/
	11
	12	#include <common.h>
	13	#include <config.h>
5ff8b354	14	#include <asm/arch/cpu.h>
0c61e6f9 AA	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	/*
	19	* orion5x_sdram_bar - reads SDRAM Base Address Register
	20	*/
	21	u32 orion5x_sdram_bar(enum memory_bank bank)
	22	{
	23	struct orion5x_ddr_addr_decode_registers *winregs =
	24	(struct orion5x_ddr_addr_decode_registers *)
286a5b25	25	ORION5X_DRAM_BASE;
0c61e6f9 AA	26
	27	u32 result = 0;
	28	u32 enable = 0x01 & winregs[bank].size;
	29
	30	if ((!enable) \|\| (bank > BANK3))
	31	return 0;
	32
	33	result = winregs[bank].base;
	34	return result;
	35	}
ab86f72c HS	36	int dram_init (void)
	37	{
	38	/* dram_init must store complete ramsize in gd->ram_size */
	39	gd->ram_size = get_ram_size(
a55d23cc	40	(long *) orion5x_sdram_bar(0),
ab86f72c HS	41	CONFIG_MAX_RAM_BANK_SIZE);
	42	return 0;
	43	}
	44
76b00aca	45	int dram_init_banksize(void)
ab86f72c HS	46	{
	47	int i;
	48
	49	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
	50	gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
	51	gd->bd->bi_dram[i].size = get_ram_size(
a55d23cc	52	(long *) (gd->bd->bi_dram[i].start),
ab86f72c HS	53	CONFIG_MAX_RAM_BANK_SIZE);
ab86f72c HS	54	}
76b00aca SG	55
76b00aca SG	56	return 0;
ab86f72c	57	}