[people/ms/u-boot.git] / arch / arm / mach-rockchip / rk3288-board-spl.c

/*
 * (C) Copyright 2015 Google, Inc
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
#include <led.h>
#include <malloc.h>
#include <ram.h>
#include <spl.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/sdram.h>
#include <asm/arch/sdram_common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
#include <dm/test.h>
#include <dm/util.h>
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>

DECLARE_GLOBAL_DATA_PTR;

u32 spl_boot_device(void)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	const void *blob = gd->fdt_blob;
	struct udevice *dev;
	const char *bootdev;
	int node;
	int ret;

	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
	debug("Boot device %s\n", bootdev);
	if (!bootdev)
		goto fallback;

	node = fdt_path_offset(blob, bootdev);
	if (node < 0) {
		debug("node=%d\n", node);
		goto fallback;
	}
	ret = device_get_global_by_of_offset(node, &dev);
	if (ret) {
		debug("device at node %s/%d not found: %d\n", bootdev, node,
		      ret);
		goto fallback;
	}
	debug("Found device %s\n", dev->name);
	switch (device_get_uclass_id(dev)) {
	case UCLASS_SPI_FLASH:
		return BOOT_DEVICE_SPI;
	case UCLASS_MMC:
		return BOOT_DEVICE_MMC1;
	default:
		debug("Booting from device uclass '%s' not supported\n",
		      dev_get_uclass_name(dev));
	}

fallback:
#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
	return BOOT_DEVICE_SPI;
#endif
	return BOOT_DEVICE_MMC1;
}

#ifdef CONFIG_SPL_MMC_SUPPORT
static int configure_emmc(struct udevice *pinctrl)
{
#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)

	struct gpio_desc desc;
	int ret;

	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);

	/*
	 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
	 * use the EMMC_PWREN setting.
	 */
	ret = dm_gpio_lookup_name("D9", &desc);
	if (ret) {
		debug("gpio ret=%d\n", ret);
		return ret;
	}
	ret = dm_gpio_request(&desc, "emmc_pwren");
	if (ret) {
		debug("gpio_request ret=%d\n", ret);
		return ret;
	}
	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
	if (ret) {
		debug("gpio dir ret=%d\n", ret);
		return ret;
	}
	ret = dm_gpio_set_value(&desc, 1);
	if (ret) {
		debug("gpio value ret=%d\n", ret);
		return ret;
	}
#endif
	return 0;
}
#endif

#if !defined(CONFIG_SPL_OF_PLATDATA)
static int phycore_init(void)
{
	struct udevice *pmic;
	int ret;

	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
	if (ret)
		return ret;

#if defined(CONFIG_SPL_POWER_SUPPORT)
	/* Increase USB input current to 2A */
	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
	if (ret)
		return ret;

	/* Close charger when USB lower then 3.26V */
	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
	if (ret)
		return ret;
#endif

	return 0;
}
#endif

void board_init_f(ulong dummy)
{
	struct udevice *pinctrl;
	struct udevice *dev;
	int ret;

	/* Example code showing how to enable the debug UART on RK3288 */
#include <asm/arch/grf_rk3288.h>
	/* Enable early UART on the RK3288 */
#define GRF_BASE	0xff770000
	struct rk3288_grf * const grf = (void *)GRF_BASE;

	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
		     GPIO7C6_MASK << GPIO7C6_SHIFT,
		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
	/*
	 * Debug UART can be used from here if required:
	 *
	 * debug_uart_init();
	 * printch('a');
	 * printhex8(0x1234);
	 * printascii("string");
	 */
	debug_uart_init();
	debug("\nspl:debug uart enabled in %s\n", __func__);
	ret = spl_early_init();
	if (ret) {
		debug("spl_early_init() failed: %d\n", ret);
		hang();
	}

	rockchip_timer_init();
	configure_l2ctlr();

	ret = rockchip_get_clk(&dev);
	if (ret) {
		debug("CLK init failed: %d\n", ret);
		return;
	}

	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	if (ret) {
		debug("Pinctrl init failed: %d\n", ret);
		return;
	}

#if !defined(CONFIG_SPL_OF_PLATDATA)
	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
		ret = phycore_init();
		if (ret) {
			debug("Failed to set up phycore power settings: %d\n",
			      ret);
			return;
		}
	}
#endif

#if !defined(CONFIG_SUPPORT_TPL)
	debug("\nspl:init dram\n");
	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	if (ret) {
		debug("DRAM init failed: %d\n", ret);
		return;
	}
#endif

#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}

static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
	struct udevice *dev;
	char *led_name;
	int ret;

	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
	if (!led_name)
		return 0;
	ret = led_get_by_label(led_name, &dev);
	if (ret) {
		debug("%s: get=%d\n", __func__, ret);
		return ret;
	}
	ret = led_set_on(dev, 1);
	if (ret)
		return ret;
#endif

	return 0;
}

void spl_board_init(void)
{
	struct udevice *pinctrl;
	int ret;

	ret = setup_led();

	if (ret) {
		debug("LED ret=%d\n", ret);
		hang();
	}

	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	if (ret) {
		debug("%s: Cannot find pinctrl device\n", __func__);
		goto err;
	}

#ifdef CONFIG_SPL_MMC_SUPPORT
	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
	if (ret) {
		debug("%s: Failed to set up SD card\n", __func__);
		goto err;
	}
	ret = configure_emmc(pinctrl);
	if (ret) {
		debug("%s: Failed to set up eMMC\n", __func__);
		goto err;
	}
#endif

	/* Enable debug UART */
	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
	if (ret) {
		debug("%s: Failed to set up console UART\n", __func__);
		goto err;
	}

	preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
	return;
err:
	printf("spl_board_init: Error %d\n", ret);

	/* No way to report error here */
	hang();
}

#ifdef CONFIG_SPL_OS_BOOT

#define PMU_BASE		0xff730000
int dram_init_banksize(void)
{
	struct rk3288_pmu *const pmu = (void *)PMU_BASE;
	size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);

	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = size;

	return 0;
}
#endif
Commit	Line	Data
2444dae5 SG	1	/*
	2	* (C) Copyright 2015 Google, Inc
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <debug_uart.h>
	9	#include <dm.h>
	10	#include <fdtdec.h>
bafcf2db	11	#include <i2c.h>
2444dae5 SG	12	#include <led.h>
	13	#include <malloc.h>
	14	#include <ram.h>
	15	#include <spl.h>
	16	#include <asm/gpio.h>
	17	#include <asm/io.h>
aade077e	18	#include <asm/arch/bootrom.h>
2444dae5 SG	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/hardware.h>
	21	#include <asm/arch/periph.h>
2ee3021a	22	#include <asm/arch/pmu_rk3288.h>
2444dae5	23	#include <asm/arch/sdram.h>
2ee3021a	24	#include <asm/arch/sdram_common.h>
a982d515	25	#include <asm/arch/sys_proto.h>
cc2244b8	26	#include <asm/arch/timer.h>
2444dae5 SG	27	#include <dm/pinctrl.h>
	28	#include <dm/root.h>
	29	#include <dm/test.h>
	30	#include <dm/util.h>
	31	#include <power/regulator.h>
bafcf2db	32	#include <power/rk8xx_pmic.h>
2444dae5 SG	33
	34	DECLARE_GLOBAL_DATA_PTR;
	35
	36	u32 spl_boot_device(void)
	37	{
6afc4661	38	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
2444dae5 SG	39	const void *blob = gd->fdt_blob;
	40	struct udevice *dev;
	41	const char *bootdev;
	42	int node;
	43	int ret;
	44
	45	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
	46	debug("Boot device %s\n", bootdev);
	47	if (!bootdev)
	48	goto fallback;
	49
	50	node = fdt_path_offset(blob, bootdev);
	51	if (node < 0) {
	52	debug("node=%d\n", node);
	53	goto fallback;
	54	}
	55	ret = device_get_global_by_of_offset(node, &dev);
	56	if (ret) {
	57	debug("device at node %s/%d not found: %d\n", bootdev, node,
	58	ret);
	59	goto fallback;
	60	}
	61	debug("Found device %s\n", dev->name);
	62	switch (device_get_uclass_id(dev)) {
	63	case UCLASS_SPI_FLASH:
	64	return BOOT_DEVICE_SPI;
	65	case UCLASS_MMC:
	66	return BOOT_DEVICE_MMC1;
	67	default:
	68	debug("Booting from device uclass '%s' not supported\n",
	69	dev_get_uclass_name(dev));
	70	}
	71
	72	fallback:
e70408c0	73	#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) \|\| \
c420ef67 SG	74	defined(CONFIG_TARGET_CHROMEBIT_MICKEY) \|\| \
c420ef67 SG	75	defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
c8816d14	76	return BOOT_DEVICE_SPI;
6afc4661	77	#endif
2444dae5 SG	78	return BOOT_DEVICE_MMC1;
	79	}
	80
f23cf909	81	#ifdef CONFIG_SPL_MMC_SUPPORT
2444dae5 SG	82	static int configure_emmc(struct udevice *pinctrl)
2444dae5 SG	83	{
d7ca67b7	84	#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
5051a77b	85
2444dae5 SG	86	struct gpio_desc desc;
	87	int ret;
	88
	89	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
	90
	91	/*
	92	* TODO(sjg@chromium.org): Pick this up from device tree or perhaps
	93	* use the EMMC_PWREN setting.
	94	*/
	95	ret = dm_gpio_lookup_name("D9", &desc);
	96	if (ret) {
	97	debug("gpio ret=%d\n", ret);
	98	return ret;
	99	}
	100	ret = dm_gpio_request(&desc, "emmc_pwren");
	101	if (ret) {
	102	debug("gpio_request ret=%d\n", ret);
	103	return ret;
	104	}
	105	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
	106	if (ret) {
	107	debug("gpio dir ret=%d\n", ret);
	108	return ret;
	109	}
	110	ret = dm_gpio_set_value(&desc, 1);
	111	if (ret) {
	112	debug("gpio value ret=%d\n", ret);
	113	return ret;
	114	}
5051a77b	115	#endif
2444dae5 SG	116	return 0;
2444dae5 SG	117	}
f23cf909	118	#endif
aade077e	119
bafcf2db WE	120	#if !defined(CONFIG_SPL_OF_PLATDATA)
	121	static int phycore_init(void)
	122	{
	123	struct udevice *pmic;
	124	int ret;
	125
	126	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
	127	if (ret)
	128	return ret;
	129
	130	#if defined(CONFIG_SPL_POWER_SUPPORT)
	131	/* Increase USB input current to 2A */
	132	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
	133	if (ret)
	134	return ret;
	135
	136	/* Close charger when USB lower then 3.26V */
	137	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
	138	if (ret)
	139	return ret;
	140	#endif
	141
	142	return 0;
	143	}
	144	#endif
	145
2444dae5 SG	146	void board_init_f(ulong dummy)
	147	{
	148	struct udevice *pinctrl;
	149	struct udevice *dev;
	150	int ret;
	151
	152	/* Example code showing how to enable the debug UART on RK3288 */
2444dae5 SG	153	#include <asm/arch/grf_rk3288.h>
	154	/* Enable early UART on the RK3288 */
	155	#define GRF_BASE 0xff770000
	156	struct rk3288_grf * const grf = (void *)GRF_BASE;
	157
	158	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT \|
	159	GPIO7C6_MASK << GPIO7C6_SHIFT,
	160	GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT \|
	161	GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
	162	/*
	163	* Debug UART can be used from here if required:
	164	*
	165	* debug_uart_init();
	166	* printch('a');
	167	* printhex8(0x1234);
	168	* printascii("string");
	169	*/
	170	debug_uart_init();
7474bbe8	171	debug("\nspl:debug uart enabled in %s\n", __func__);
73976056	172	ret = spl_early_init();
2444dae5	173	if (ret) {
73976056	174	debug("spl_early_init() failed: %d\n", ret);
2444dae5 SG	175	hang();
	176	}
	177
cc2244b8	178	rockchip_timer_init();
2444dae5 SG	179	configure_l2ctlr();
2444dae5 SG	180
c3aad6f6	181	ret = rockchip_get_clk(&dev);
2444dae5 SG	182	if (ret) {
	183	debug("CLK init failed: %d\n", ret);
	184	return;
	185	}
	186
	187	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	188	if (ret) {
	189	debug("Pinctrl init failed: %d\n", ret);
	190	return;
	191	}
bafcf2db WE	192
	193	#if !defined(CONFIG_SPL_OF_PLATDATA)
	194	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
	195	ret = phycore_init();
	196	if (ret) {
	197	debug("Failed to set up phycore power settings: %d\n",
	198	ret);
	199	return;
	200	}
	201	}
	202	#endif
	203
532cb7f5	204	#if !defined(CONFIG_SUPPORT_TPL)
7474bbe8	205	debug("\nspl:init dram\n");
2444dae5 SG	206	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
	207	if (ret) {
	208	debug("DRAM init failed: %d\n", ret);
	209	return;
	210	}
532cb7f5 JT	211	#endif
532cb7f5 JT	212
ee14d29d	213	#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
b82bd1f8	214	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
b47ea792	215	#endif
2444dae5 SG	216	}
	217
	218	static int setup_led(void)
	219	{
	220	#ifdef CONFIG_SPL_LED
	221	struct udevice *dev;
	222	char *led_name;
	223	int ret;
	224
	225	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
	226	if (!led_name)
	227	return 0;
	228	ret = led_get_by_label(led_name, &dev);
	229	if (ret) {
	230	debug("%s: get=%d\n", __func__, ret);
	231	return ret;
	232	}
	233	ret = led_set_on(dev, 1);
	234	if (ret)
	235	return ret;
	236	#endif
	237
	238	return 0;
	239	}
	240
	241	void spl_board_init(void)
	242	{
	243	struct udevice *pinctrl;
	244	int ret;
	245
	246	ret = setup_led();
	247
	248	if (ret) {
	249	debug("LED ret=%d\n", ret);
	250	hang();
	251	}
	252
	253	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
	254	if (ret) {
	255	debug("%s: Cannot find pinctrl device\n", __func__);
	256	goto err;
	257	}
5051a77b	258
f23cf909	259	#ifdef CONFIG_SPL_MMC_SUPPORT
5051a77b	260	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
	261	if (ret) {
	262	debug("%s: Failed to set up SD card\n", __func__);
	263	goto err;
	264	}
	265	ret = configure_emmc(pinctrl);
	266	if (ret) {
	267	debug("%s: Failed to set up eMMC\n", __func__);
	268	goto err;
2444dae5	269	}
f23cf909	270	#endif
2444dae5 SG	271
	272	/* Enable debug UART */
	273	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
	274	if (ret) {
	275	debug("%s: Failed to set up console UART\n", __func__);
	276	goto err;
	277	}
	278
	279	preloader_console_init();
ee14d29d	280	#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
b82bd1f8	281	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
427351dc	282	#endif
2444dae5 SG	283	return;
	284	err:
	285	printf("spl_board_init: Error %d\n", ret);
	286
	287	/* No way to report error here */
	288	hang();
	289	}
2ee3021a JT	290
	291	#ifdef CONFIG_SPL_OS_BOOT
	292
	293	#define PMU_BASE 0xff730000
	294	int dram_init_banksize(void)
	295	{
	296	struct rk3288_pmu const pmu = (void )PMU_BASE;
	297	size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
	298
	299	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	300	gd->bd->bi_dram[0].size = size;
	301
	302	return 0;
	303	}
	304	#endif