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Commit | Line | Data |
---|---|---|
7865f4b0 MY |
1 | if ARCH_SOCFPGA |
2 | ||
cd9b7317 MV |
3 | config TARGET_SOCFPGA_ARRIA5 |
4 | bool | |
5 | ||
6 | config TARGET_SOCFPGA_CYCLONE5 | |
7 | bool | |
8 | ||
7865f4b0 MY |
9 | choice |
10 | prompt "Altera SOCFPGA board select" | |
a26cd049 | 11 | optional |
7865f4b0 | 12 | |
cd9b7317 MV |
13 | config TARGET_SOCFPGA_ARRIA5_SOCDK |
14 | bool "Altera SOCFPGA SoCDK (Arria V)" | |
15 | select TARGET_SOCFPGA_ARRIA5 | |
7865f4b0 | 16 | |
cd9b7317 MV |
17 | config TARGET_SOCFPGA_CYCLONE5_SOCDK |
18 | bool "Altera SOCFPGA SoCDK (Cyclone V)" | |
19 | select TARGET_SOCFPGA_CYCLONE5 | |
7865f4b0 | 20 | |
d88995a8 MV |
21 | config TARGET_SOCFPGA_DENX_MCVEVK |
22 | bool "DENX MCVEVK (Cyclone V)" | |
23 | select TARGET_SOCFPGA_CYCLONE5 | |
24 | ||
856b30da MV |
25 | config TARGET_SOCFPGA_EBV_SOCRATES |
26 | bool "EBV SoCrates (Cyclone V)" | |
27 | select TARGET_SOCFPGA_CYCLONE5 | |
28 | ||
55c7a765 DN |
29 | config TARGET_SOCFPGA_TERASIC_DE0_NANO |
30 | bool "Terasic DE0-Nano-Atlas (Cyclone V)" | |
31 | select TARGET_SOCFPGA_CYCLONE5 | |
32 | ||
952caa28 MV |
33 | config TARGET_SOCFPGA_TERASIC_SOCKIT |
34 | bool "Terasic SoCkit (Cyclone V)" | |
35 | select TARGET_SOCFPGA_CYCLONE5 | |
36 | ||
7865f4b0 MY |
37 | endchoice |
38 | ||
39 | config SYS_BOARD | |
f0892401 MV |
40 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
41 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
55c7a765 | 42 | default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
d88995a8 | 43 | default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
952caa28 | 44 | default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
856b30da | 45 | default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
7865f4b0 MY |
46 | |
47 | config SYS_VENDOR | |
cd9b7317 MV |
48 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
49 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
d88995a8 | 50 | default "denx" if TARGET_SOCFPGA_DENX_MCVEVK |
856b30da | 51 | default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES |
55c7a765 | 52 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
952caa28 | 53 | default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT |
7865f4b0 MY |
54 | |
55 | config SYS_SOC | |
56 | default "socfpga" | |
57 | ||
58 | config SYS_CONFIG_NAME | |
3cbc7b87 DN |
59 | default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
60 | default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
55c7a765 | 61 | default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
d88995a8 | 62 | default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
952caa28 | 63 | default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
856b30da | 64 | default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
7865f4b0 MY |
65 | |
66 | endif |