projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7865f4b0 MY |
1 | if ARCH_SOCFPGA |
| 2 | ||
| 77d2f7f5 SG |
3 | config SPL_LIBCOMMON_SUPPORT |
| 4 | default y | |
| 5 | ||
| 1646eba8 SG |
6 | config SPL_LIBDISK_SUPPORT |
| 7 | default y | |
| 8 | ||
| cc4288ef SG |
9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y | |
| 11 | ||
| cd9b7317 MV |
12 | config TARGET_SOCFPGA_ARRIA5 |
| 13 | bool | |
| ed77aeb5 | 14 | select TARGET_SOCFPGA_GEN5 |
| cd9b7317 MV |
15 | |
| 16 | config TARGET_SOCFPGA_CYCLONE5 | |
| 17 | bool | |
| ed77aeb5 DN |
18 | select TARGET_SOCFPGA_GEN5 |
| 19 | ||
| 20 | config TARGET_SOCFPGA_GEN5 | |
| 21 | bool | |
| cd9b7317 | 22 | |
| 7865f4b0 MY |
23 | choice |
| 24 | prompt "Altera SOCFPGA board select" | |
| a26cd049 | 25 | optional |
| 7865f4b0 | 26 | |
| cd9b7317 MV |
27 | config TARGET_SOCFPGA_ARRIA5_SOCDK |
| 28 | bool "Altera SOCFPGA SoCDK (Arria V)" | |
| 29 | select TARGET_SOCFPGA_ARRIA5 | |
| 7865f4b0 | 30 | |
| cd9b7317 MV |
31 | config TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 32 | bool "Altera SOCFPGA SoCDK (Cyclone V)" | |
| 33 | select TARGET_SOCFPGA_CYCLONE5 | |
| 7865f4b0 | 34 | |
| d88995a8 MV |
35 | config TARGET_SOCFPGA_DENX_MCVEVK |
| 36 | bool "DENX MCVEVK (Cyclone V)" | |
| 37 | select TARGET_SOCFPGA_CYCLONE5 | |
| 38 | ||
| 856b30da MV |
39 | config TARGET_SOCFPGA_EBV_SOCRATES |
| 40 | bool "EBV SoCrates (Cyclone V)" | |
| 41 | select TARGET_SOCFPGA_CYCLONE5 | |
| 42 | ||
| 35546f6f PM |
43 | config TARGET_SOCFPGA_IS1 |
| 44 | bool "IS1 (Cyclone V)" | |
| 45 | select TARGET_SOCFPGA_CYCLONE5 | |
| 46 | ||
| 569a191a MV |
47 | config TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 48 | bool "samtec VIN|ING FPGA (Cyclone V)" | |
| 49 | select TARGET_SOCFPGA_CYCLONE5 | |
| 50 | ||
| cf0a8dab MV |
51 | config TARGET_SOCFPGA_SR1500 |
| 52 | bool "SR1500 (Cyclone V)" | |
| 53 | select TARGET_SOCFPGA_CYCLONE5 | |
| 54 | ||
| 55c7a765 DN |
55 | config TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 56 | bool "Terasic DE0-Nano-Atlas (Cyclone V)" | |
| 57 | select TARGET_SOCFPGA_CYCLONE5 | |
| 58 | ||
| 952caa28 MV |
59 | config TARGET_SOCFPGA_TERASIC_SOCKIT |
| 60 | bool "Terasic SoCkit (Cyclone V)" | |
| 61 | select TARGET_SOCFPGA_CYCLONE5 | |
| 62 | ||
| 7865f4b0 MY |
63 | endchoice |
| 64 | ||
| 65 | config SYS_BOARD | |
| f0892401 MV |
66 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 67 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| 55c7a765 | 68 | default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 35546f6f | 69 | default "is1" if TARGET_SOCFPGA_IS1 |
| d88995a8 | 70 | default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
| 952caa28 | 71 | default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 856b30da | 72 | default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
| ae9996c8 | 73 | default "sr1500" if TARGET_SOCFPGA_SR1500 |
| 569a191a | 74 | default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 7865f4b0 MY |
75 | |
| 76 | config SYS_VENDOR | |
| cd9b7317 MV |
77 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 78 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| d88995a8 | 79 | default "denx" if TARGET_SOCFPGA_DENX_MCVEVK |
| 856b30da | 80 | default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES |
| 569a191a | 81 | default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 55c7a765 | 82 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 952caa28 | 83 | default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 7865f4b0 MY |
84 | |
| 85 | config SYS_SOC | |
| 86 | default "socfpga" | |
| 87 | ||
| 88 | config SYS_CONFIG_NAME | |
| 3cbc7b87 DN |
89 | default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 90 | default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| 55c7a765 | 91 | default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 35546f6f | 92 | default "socfpga_is1" if TARGET_SOCFPGA_IS1 |
| d88995a8 | 93 | default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
| 952caa28 | 94 | default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 856b30da | 95 | default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
| ae9996c8 | 96 | default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 |
| 569a191a | 97 | default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 7865f4b0 MY |
98 | |
| 99 | endif |