[people/ms/u-boot.git] / arch / arm / mach-socfpga / Makefile

#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
#
# SPDX-License-Identifier:	GPL-2.0+
#

obj-y	+= board.o
obj-y	+= clock_manager.o
obj-y	+= misc.o
obj-y	+= reset_manager.o
obj-y	+= timer.o

ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y	+= clock_manager_gen5.o
obj-y	+= misc_gen5.o
obj-y	+= reset_manager_gen5.o
obj-y	+= scan_manager.o
obj-y	+= system_manager_gen5.o
obj-y	+= wrap_pll_config.o
obj-y	+= fpga_manager.o
endif

ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y	+= clock_manager_arria10.o
obj-y	+= misc_arria10.o
obj-y	+= pinmux_arria10.o
obj-y	+= reset_manager_arria10.o
endif

ifdef CONFIG_SPL_BUILD
obj-y	+= spl.o
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y	+= freeze_controller.o
obj-y	+= wrap_iocsr_config.o
obj-y	+= wrap_pinmux_config.o
obj-y	+= wrap_sdram_config.o
endif
endif

ifdef CONFIG_TARGET_SOCFPGA_GEN5
# QTS-generated config file wrappers
CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_pinmux_config.o	+= -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_pll_config.o	+= -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_sdram_config.o	+= -I$(srctree)/board/$(BOARDDIR)
endif
Commit	Line	Data
77754408 DN	1	#
	2	# (C) Copyright 2000-2003
	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	#
d89e979c	5	# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
77754408	6	#
1a459660	7	# SPDX-License-Identifier: GPL-2.0+
77754408 DN	8	#
77754408 DN	9
d89e979c LFT	10	obj-y += board.o
d89e979c LFT	11	obj-y += clock_manager.o
d89e979c LFT	12	obj-y += misc.o
	13	obj-y += reset_manager.o
	14	obj-y += timer.o
e5ad7d98	15
d89e979c LFT	16	ifdef CONFIG_TARGET_SOCFPGA_GEN5
	17	obj-y += clock_manager_gen5.o
	18	obj-y += misc_gen5.o
	19	obj-y += reset_manager_gen5.o
	20	obj-y += scan_manager.o
	21	obj-y += system_manager_gen5.o
	22	obj-y += wrap_pll_config.o
6867e19a	23	obj-y += fpga_manager.o
d89e979c	24	endif
827e6a7e	25
d89e979c LFT	26	ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
	27	obj-y += clock_manager_arria10.o
	28	obj-y += misc_arria10.o
	29	obj-y += pinmux_arria10.o
	30	obj-y += reset_manager_arria10.o
	31	endif
ca62d2e1	32
d89e979c LFT	33	ifdef CONFIG_SPL_BUILD
	34	obj-y += spl.o
	35	ifdef CONFIG_TARGET_SOCFPGA_GEN5
	36	obj-y += freeze_controller.o
	37	obj-y += wrap_iocsr_config.o
	38	obj-y += wrap_pinmux_config.o
	39	obj-y += wrap_sdram_config.o
	40	endif
	41	endif
	42
	43	ifdef CONFIG_TARGET_SOCFPGA_GEN5
ca62d2e1	44	# QTS-generated config file wrappers
ca62d2e1 MV	45	CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
	46	CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
	47	CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
	48	CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
d89e979c	49	endif