[people/ms/u-boot.git] / arch / arm / mach-stm32 / stm32f4 / clock.c

/*
 * (C) Copyright 2015
 * Kamil Lulko, <kamil.lulko@gmail.com>
 *
 * (C) Copyright 2014
 * STMicroelectronics
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <stm32_rcc.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>

#define RCC_CR_HSION		(1 << 0)
#define RCC_CR_HSEON		(1 << 16)
#define RCC_CR_HSERDY		(1 << 17)
#define RCC_CR_HSEBYP		(1 << 18)
#define RCC_CR_CSSON		(1 << 19)
#define RCC_CR_PLLON		(1 << 24)
#define RCC_CR_PLLRDY		(1 << 25)

#define RCC_PLLCFGR_PLLM_MASK	0x3F
#define RCC_PLLCFGR_PLLN_MASK	0x7FC0
#define RCC_PLLCFGR_PLLP_MASK	0x30000
#define RCC_PLLCFGR_PLLQ_MASK	0xF000000
#define RCC_PLLCFGR_PLLSRC	(1 << 22)
#define RCC_PLLCFGR_PLLN_SHIFT	6
#define RCC_PLLCFGR_PLLP_SHIFT	16
#define RCC_PLLCFGR_PLLQ_SHIFT	24

#define RCC_CFGR_AHB_PSC_MASK	0xF0
#define RCC_CFGR_APB1_PSC_MASK	0x1C00
#define RCC_CFGR_APB2_PSC_MASK	0xE000
#define RCC_CFGR_SW0		(1 << 0)
#define RCC_CFGR_SW1		(1 << 1)
#define RCC_CFGR_SW_MASK	0x3
#define RCC_CFGR_SW_HSI		0
#define RCC_CFGR_SW_HSE		RCC_CFGR_SW0
#define RCC_CFGR_SW_PLL		RCC_CFGR_SW1
#define RCC_CFGR_SWS0		(1 << 2)
#define RCC_CFGR_SWS1		(1 << 3)
#define RCC_CFGR_SWS_MASK	0xC
#define RCC_CFGR_SWS_HSI	0
#define RCC_CFGR_SWS_HSE	RCC_CFGR_SWS0
#define RCC_CFGR_SWS_PLL	RCC_CFGR_SWS1
#define RCC_CFGR_HPRE_SHIFT	4
#define RCC_CFGR_PPRE1_SHIFT	10
#define RCC_CFGR_PPRE2_SHIFT	13

#define RCC_APB1ENR_PWREN	(1 << 28)

/*
 * RCC USART specific definitions
 */
#define RCC_ENR_USART1EN		(1 << 4)
#define RCC_ENR_USART2EN		(1 << 17)
#define RCC_ENR_USART3EN		(1 << 18)
#define RCC_ENR_USART6EN		(1 <<  5)

#define PWR_CR_VOS0		(1 << 14)
#define PWR_CR_VOS1		(1 << 15)
#define PWR_CR_VOS_MASK		0xC000
#define PWR_CR_VOS_SCALE_MODE_1	(PWR_CR_VOS0 | PWR_CR_VOS1)
#define PWR_CR_VOS_SCALE_MODE_2	(PWR_CR_VOS1)
#define PWR_CR_VOS_SCALE_MODE_3	(PWR_CR_VOS0)

/*
 * RCC GPIO specific definitions
 */
#define RCC_ENR_GPIO_A_EN	(1 << 0)
#define RCC_ENR_GPIO_B_EN	(1 << 1)
#define RCC_ENR_GPIO_C_EN	(1 << 2)
#define RCC_ENR_GPIO_D_EN	(1 << 3)
#define RCC_ENR_GPIO_E_EN	(1 << 4)
#define RCC_ENR_GPIO_F_EN	(1 << 5)
#define RCC_ENR_GPIO_G_EN	(1 << 6)
#define RCC_ENR_GPIO_H_EN	(1 << 7)
#define RCC_ENR_GPIO_I_EN	(1 << 8)
#define RCC_ENR_GPIO_J_EN	(1 << 9)
#define RCC_ENR_GPIO_K_EN	(1 << 10)

#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
#if (CONFIG_STM32_HSE_HZ == 8000000)
#if (CONFIG_SYS_CLK_FREQ == 180000000)
/* 180 MHz */
struct pll_psc sys_pll_psc = {
	.pll_m = 8,
	.pll_n = 360,
	.pll_p = 2,
	.pll_q = 8,
	.ahb_psc = AHB_PSC_1,
	.apb1_psc = APB_PSC_4,
	.apb2_psc = APB_PSC_2
};
#else
/* default 168 MHz */
struct pll_psc sys_pll_psc = {
	.pll_m = 8,
	.pll_n = 336,
	.pll_p = 2,
	.pll_q = 7,
	.ahb_psc = AHB_PSC_1,
	.apb1_psc = APB_PSC_4,
	.apb2_psc = APB_PSC_2
};
#endif
#else
#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
#endif
#endif

int configure_clocks(void)
{
	/* Reset RCC configuration */
	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
		| RCC_CR_PLLON));
	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
	writel(0, &STM32_RCC->cir); /* Disable all interrupts */

	/* Configure for HSE+PLL operation */
	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
		;

	/* Enable high performance mode, System frequency up to 180 MHz */
	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
	writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);

	setbits_le32(&STM32_RCC->cfgr, ((
		sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
		| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
		| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));

	writel(sys_pll_psc.pll_m
		| (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
		| (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
		| (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
		&STM32_RCC->pllcfgr);
	setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);

	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);

	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
		;

	stm32_flash_latency_cfg(5);
	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);

	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
			RCC_CFGR_SWS_PLL)
		;

	return 0;
}

unsigned long clock_get(enum clock clck)
{
	u32 sysclk = 0;
	u32 shift = 0;
	/* Prescaler table lookups for clock computation */
	u8 ahb_psc_table[16] = {
		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
	};
	u8 apb_psc_table[8] = {
		0, 0, 0, 0, 1, 2, 3, 4
	};

	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
			RCC_CFGR_SWS_PLL) {
		u16 pllm, plln, pllp;
		pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
		plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
			>> RCC_PLLCFGR_PLLN_SHIFT);
		pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
	}

	switch (clck) {
	case CLOCK_CORE:
		return sysclk;
		break;
	case CLOCK_AHB:
		shift = ahb_psc_table[(
			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
			>> RCC_CFGR_HPRE_SHIFT)];
		return sysclk >>= shift;
		break;
	case CLOCK_APB1:
		shift = apb_psc_table[(
			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
			>> RCC_CFGR_PPRE1_SHIFT)];
		return sysclk >>= shift;
		break;
	case CLOCK_APB2:
		shift = apb_psc_table[(
			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
			>> RCC_CFGR_PPRE2_SHIFT)];
		return sysclk >>= shift;
		break;
	default:
		return 0;
		break;
	}
}

void clock_setup(int peripheral)
{
	switch (peripheral) {
	case USART1_CLOCK_CFG:
		setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
		break;
	case GPIO_A_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
		break;
	case GPIO_B_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
		break;
	case GPIO_C_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
		break;
	case GPIO_D_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
		break;
	case GPIO_E_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
		break;
	case GPIO_F_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
		break;
	case GPIO_G_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
		break;
	case GPIO_H_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
		break;
	case GPIO_I_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
		break;
	case GPIO_J_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
		break;
	case GPIO_K_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
		break;
	default:
		break;
	}
}
Commit	Line	Data
eaaa4f7e	1	/*
eaaa4f7e	2	* (C) Copyright 2015
5be93569	3	* Kamil Lulko, <kamil.lulko@gmail.com>
eaaa4f7e	4	*
	5	* (C) Copyright 2014
	6	* STMicroelectronics
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
014a953c	12	#include <stm32_rcc.h>
eaaa4f7e	13	#include <asm/io.h>
eaaa4f7e	14	#include <asm/arch/stm32.h>
dffceb4b	15	#include <asm/arch/stm32_periph.h>
eaaa4f7e	16
	17	#define RCC_CR_HSION (1 << 0)
	18	#define RCC_CR_HSEON (1 << 16)
	19	#define RCC_CR_HSERDY (1 << 17)
	20	#define RCC_CR_HSEBYP (1 << 18)
	21	#define RCC_CR_CSSON (1 << 19)
	22	#define RCC_CR_PLLON (1 << 24)
	23	#define RCC_CR_PLLRDY (1 << 25)
	24
	25	#define RCC_PLLCFGR_PLLM_MASK 0x3F
	26	#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
	27	#define RCC_PLLCFGR_PLLP_MASK 0x30000
	28	#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
	29	#define RCC_PLLCFGR_PLLSRC (1 << 22)
	30	#define RCC_PLLCFGR_PLLN_SHIFT 6
	31	#define RCC_PLLCFGR_PLLP_SHIFT 16
	32	#define RCC_PLLCFGR_PLLQ_SHIFT 24
	33
	34	#define RCC_CFGR_AHB_PSC_MASK 0xF0
	35	#define RCC_CFGR_APB1_PSC_MASK 0x1C00
	36	#define RCC_CFGR_APB2_PSC_MASK 0xE000
	37	#define RCC_CFGR_SW0 (1 << 0)
	38	#define RCC_CFGR_SW1 (1 << 1)
	39	#define RCC_CFGR_SW_MASK 0x3
	40	#define RCC_CFGR_SW_HSI 0
	41	#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
	42	#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
	43	#define RCC_CFGR_SWS0 (1 << 2)
	44	#define RCC_CFGR_SWS1 (1 << 3)
	45	#define RCC_CFGR_SWS_MASK 0xC
	46	#define RCC_CFGR_SWS_HSI 0
	47	#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
	48	#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
	49	#define RCC_CFGR_HPRE_SHIFT 4
	50	#define RCC_CFGR_PPRE1_SHIFT 10
	51	#define RCC_CFGR_PPRE2_SHIFT 13
	52
	53	#define RCC_APB1ENR_PWREN (1 << 28)
	54
dffceb4b VM	55	/*
	56	* RCC USART specific definitions
	57	*/
	58	#define RCC_ENR_USART1EN (1 << 4)
	59	#define RCC_ENR_USART2EN (1 << 17)
	60	#define RCC_ENR_USART3EN (1 << 18)
	61	#define RCC_ENR_USART6EN (1 << 5)
	62
eaaa4f7e	63	#define PWR_CR_VOS0 (1 << 14)
	64	#define PWR_CR_VOS1 (1 << 15)
	65	#define PWR_CR_VOS_MASK 0xC000
	66	#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 \| PWR_CR_VOS1)
	67	#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
	68	#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
	69
14cec061 VM	70	/*
	71	* RCC GPIO specific definitions
	72	*/
	73	#define RCC_ENR_GPIO_A_EN (1 << 0)
	74	#define RCC_ENR_GPIO_B_EN (1 << 1)
	75	#define RCC_ENR_GPIO_C_EN (1 << 2)
	76	#define RCC_ENR_GPIO_D_EN (1 << 3)
	77	#define RCC_ENR_GPIO_E_EN (1 << 4)
	78	#define RCC_ENR_GPIO_F_EN (1 << 5)
	79	#define RCC_ENR_GPIO_G_EN (1 << 6)
	80	#define RCC_ENR_GPIO_H_EN (1 << 7)
	81	#define RCC_ENR_GPIO_I_EN (1 << 8)
	82	#define RCC_ENR_GPIO_J_EN (1 << 9)
	83	#define RCC_ENR_GPIO_K_EN (1 << 10)
	84
eaaa4f7e	85	#if !defined(CONFIG_STM32_HSE_HZ)
	86	#error "CONFIG_STM32_HSE_HZ not defined!"
	87	#else
	88	#if (CONFIG_STM32_HSE_HZ == 8000000)
fffde77e AB	89	#if (CONFIG_SYS_CLK_FREQ == 180000000)
	90	/* 180 MHz */
	91	struct pll_psc sys_pll_psc = {
	92	.pll_m = 8,
	93	.pll_n = 360,
	94	.pll_p = 2,
	95	.pll_q = 8,
	96	.ahb_psc = AHB_PSC_1,
	97	.apb1_psc = APB_PSC_4,
	98	.apb2_psc = APB_PSC_2
	99	};
	100	#else
	101	/* default 168 MHz */
	102	struct pll_psc sys_pll_psc = {
eaaa4f7e	103	.pll_m = 8,
	104	.pll_n = 336,
	105	.pll_p = 2,
	106	.pll_q = 7,
	107	.ahb_psc = AHB_PSC_1,
	108	.apb1_psc = APB_PSC_4,
	109	.apb2_psc = APB_PSC_2
	110	};
fffde77e	111	#endif
eaaa4f7e	112	#else
	113	#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
	114	#endif
	115	#endif
	116
	117	int configure_clocks(void)
	118	{
	119	/* Reset RCC configuration */
	120	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
	121	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
	122	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON \| RCC_CR_CSSON
	123	\| RCC_CR_PLLON));
	124	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
	125	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
	126	writel(0, &STM32_RCC->cir); /* Disable all interrupts */
	127
	128	/* Configure for HSE+PLL operation */
	129	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
	130	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
	131	;
	132
fffde77e	133	/* Enable high performance mode, System frequency up to 180 MHz */
eaaa4f7e	134	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
	135	writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
	136
	137	setbits_le32(&STM32_RCC->cfgr, ((
fffde77e AB	138	sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
	139	\| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
	140	\| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
	141
	142	writel(sys_pll_psc.pll_m
	143	\| (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
	144	\| (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
	145	\| (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
eaaa4f7e	146	&STM32_RCC->pllcfgr);
	147	setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
	148
	149	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
	150
	151	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
	152	;
	153
9ecb0c41	154	stm32_flash_latency_cfg(5);
eaaa4f7e	155	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 \| RCC_CFGR_SW1));
	156	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
	157
	158	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
	159	RCC_CFGR_SWS_PLL)
	160	;
	161
	162	return 0;
	163	}
	164
	165	unsigned long clock_get(enum clock clck)
	166	{
	167	u32 sysclk = 0;
	168	u32 shift = 0;
	169	/* Prescaler table lookups for clock computation */
	170	u8 ahb_psc_table[16] = {
	171	0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
	172	};
	173	u8 apb_psc_table[8] = {
	174	0, 0, 0, 0, 1, 2, 3, 4
	175	};
	176
	177	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
	178	RCC_CFGR_SWS_PLL) {
	179	u16 pllm, plln, pllp;
	180	pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
	181	plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
	182	>> RCC_PLLCFGR_PLLN_SHIFT);
	183	pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
	184	>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
	185	sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
	186	}
	187
	188	switch (clck) {
	189	case CLOCK_CORE:
	190	return sysclk;
	191	break;
	192	case CLOCK_AHB:
	193	shift = ahb_psc_table[(
	194	(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
	195	>> RCC_CFGR_HPRE_SHIFT)];
	196	return sysclk >>= shift;
	197	break;
	198	case CLOCK_APB1:
	199	shift = apb_psc_table[(
	200	(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
	201	>> RCC_CFGR_PPRE1_SHIFT)];
	202	return sysclk >>= shift;
	203	break;
	204	case CLOCK_APB2:
	205	shift = apb_psc_table[(
	206	(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
	207	>> RCC_CFGR_PPRE2_SHIFT)];
	208	return sysclk >>= shift;
	209	break;
	210	default:
	211	return 0;
	212	break;
	213	}
	214	}
dffceb4b VM	215
	216	void clock_setup(int peripheral)
	217	{
	218	switch (peripheral) {
	219	case USART1_CLOCK_CFG:
	220	setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
	221	break;
14cec061 VM	222	case GPIO_A_CLOCK_CFG:
	223	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
	224	break;
	225	case GPIO_B_CLOCK_CFG:
	226	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
	227	break;
	228	case GPIO_C_CLOCK_CFG:
	229	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
	230	break;
	231	case GPIO_D_CLOCK_CFG:
	232	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
	233	break;
	234	case GPIO_E_CLOCK_CFG:
	235	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
	236	break;
	237	case GPIO_F_CLOCK_CFG:
	238	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
	239	break;
	240	case GPIO_G_CLOCK_CFG:
	241	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
	242	break;
	243	case GPIO_H_CLOCK_CFG:
	244	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
	245	break;
	246	case GPIO_I_CLOCK_CFG:
	247	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
	248	break;
	249	case GPIO_J_CLOCK_CFG:
	250	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
	251	break;
	252	case GPIO_K_CLOCK_CFG:
	253	setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
	254	break;
dffceb4b VM	255	default:
	256	break;
	257	}
	258	}