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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
b529993e PT |
3 | config SPL_LDSCRIPT |
4 | default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 | |
5 | ||
a4d88920 SDPP |
6 | config IDENT_STRING |
7 | default " Allwinner Technology" | |
8 | ||
bc613d85 AP |
9 | config SUNXI_HIGH_SRAM |
10 | bool | |
11 | default n | |
12 | ---help--- | |
13 | Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, | |
14 | with the first SRAM region being located at address 0. | |
15 | Some newer SoCs map the boot ROM at address 0 instead and move the | |
16 | SRAM to 64KB, just behind the mask ROM. | |
17 | Chips using the latter setup are supposed to select this option to | |
18 | adjust the addresses accordingly. | |
19 | ||
44d8ae5b HG |
20 | # Note only one of these may be selected at a time! But hidden choices are |
21 | # not supported by Kconfig | |
22 | config SUNXI_GEN_SUN4I | |
23 | bool | |
24 | ---help--- | |
25 | Select this for sunxi SoCs which have resets and clocks set up | |
26 | as the original A10 (mach-sun4i). | |
27 | ||
28 | config SUNXI_GEN_SUN6I | |
29 | bool | |
30 | ---help--- | |
31 | Select this for sunxi SoCs which have sun6i like periphery, like | |
32 | separate ahb reset control registers, custom pmic bus, new style | |
33 | watchdog, etc. | |
34 | ||
9934aba4 IZ |
35 | config SUNXI_DRAM_DW |
36 | bool | |
37 | ---help--- | |
38 | Select this for sunxi SoCs which uses a DRAM controller like the | |
39 | DesignWare controller used in H3, mainly SoCs after H3, which do | |
40 | not have official open-source DRAM initialization code, but can | |
41 | use modified H3 DRAM initialization code. | |
44d8ae5b | 42 | |
87098d70 IZ |
43 | if SUNXI_DRAM_DW |
44 | config SUNXI_DRAM_DW_16BIT | |
45 | bool | |
46 | ---help--- | |
47 | Select this for sunxi SoCs with DesignWare DRAM controller and | |
48 | have only 16-bit memory buswidth. | |
49 | ||
50 | config SUNXI_DRAM_DW_32BIT | |
51 | bool | |
52 | ---help--- | |
53 | Select this for sunxi SoCs with DesignWare DRAM controller with | |
54 | 32-bit memory buswidth. | |
55 | endif | |
56 | ||
7b82a229 AP |
57 | config MACH_SUNXI_H3_H5 |
58 | bool | |
a05a4549 | 59 | select DM_I2C |
1ae5def6 | 60 | select SUNXI_DE2 |
9934aba4 | 61 | select SUNXI_DRAM_DW |
87098d70 | 62 | select SUNXI_DRAM_DW_32BIT |
7b82a229 AP |
63 | select SUNXI_GEN_SUN6I |
64 | select SUPPORT_SPL | |
65 | ||
2c7e3b90 IC |
66 | choice |
67 | prompt "Sunxi SoC Variant" | |
3da9536e | 68 | optional |
2c7e3b90 | 69 | |
c3be2793 | 70 | config MACH_SUN4I |
2c7e3b90 IC |
71 | bool "sun4i (Allwinner A10)" |
72 | select CPU_V7 | |
85db5831 | 73 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 74 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
75 | select SUPPORT_SPL |
76 | ||
c3be2793 | 77 | config MACH_SUN5I |
2c7e3b90 IC |
78 | bool "sun5i (Allwinner A13)" |
79 | select CPU_V7 | |
85db5831 | 80 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 81 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
82 | select SUPPORT_SPL |
83 | ||
c3be2793 | 84 | config MACH_SUN6I |
2c7e3b90 IC |
85 | bool "sun6i (Allwinner A31)" |
86 | select CPU_V7 | |
cc08ea4c CYT |
87 | select CPU_V7_HAS_NONSEC |
88 | select CPU_V7_HAS_VIRT | |
217f92bb | 89 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 90 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 91 | select SUPPORT_SPL |
cc08ea4c | 92 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 93 | |
c3be2793 | 94 | config MACH_SUN7I |
2c7e3b90 IC |
95 | bool "sun7i (Allwinner A20)" |
96 | select CPU_V7 | |
ea624e19 HG |
97 | select CPU_V7_HAS_NONSEC |
98 | select CPU_V7_HAS_VIRT | |
217f92bb | 99 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 100 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 101 | select SUPPORT_SPL |
b366fb92 | 102 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 103 | |
5e6bacdb | 104 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
105 | bool "sun8i (Allwinner A23)" |
106 | select CPU_V7 | |
014414f5 CYT |
107 | select CPU_V7_HAS_NONSEC |
108 | select CPU_V7_HAS_VIRT | |
217f92bb | 109 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 110 | select SUNXI_GEN_SUN6I |
08fd1479 | 111 | select SUPPORT_SPL |
014414f5 | 112 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 113 | |
8c3dacff VP |
114 | config MACH_SUN8I_A33 |
115 | bool "sun8i (Allwinner A33)" | |
116 | select CPU_V7 | |
014414f5 CYT |
117 | select CPU_V7_HAS_NONSEC |
118 | select CPU_V7_HAS_VIRT | |
217f92bb | 119 | select ARCH_SUPPORT_PSCI |
8c3dacff VP |
120 | select SUNXI_GEN_SUN6I |
121 | select SUPPORT_SPL | |
014414f5 | 122 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 123 | |
a81b7995 CYT |
124 | config MACH_SUN8I_A83T |
125 | bool "sun8i (Allwinner A83T)" | |
126 | select CPU_V7 | |
127 | select SUNXI_GEN_SUN6I | |
128 | select SUPPORT_SPL | |
129 | ||
1c27b7dc JK |
130 | config MACH_SUN8I_H3 |
131 | bool "sun8i (Allwinner H3)" | |
132 | select CPU_V7 | |
853f6d1e CYT |
133 | select CPU_V7_HAS_NONSEC |
134 | select CPU_V7_HAS_VIRT | |
217f92bb | 135 | select ARCH_SUPPORT_PSCI |
7b82a229 | 136 | select MACH_SUNXI_H3_H5 |
853f6d1e | 137 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 138 | |
379febac CYT |
139 | config MACH_SUN8I_R40 |
140 | bool "sun8i (Allwinner R40)" | |
141 | select CPU_V7 | |
0918648d CYT |
142 | select CPU_V7_HAS_NONSEC |
143 | select CPU_V7_HAS_VIRT | |
144 | select ARCH_SUPPORT_PSCI | |
379febac | 145 | select SUNXI_GEN_SUN6I |
50ae7ae5 | 146 | select SUPPORT_SPL |
9934aba4 | 147 | select SUNXI_DRAM_DW |
87098d70 | 148 | select SUNXI_DRAM_DW_32BIT |
379febac | 149 | |
c199489f IZ |
150 | config MACH_SUN8I_V3S |
151 | bool "sun8i (Allwinner V3s)" | |
152 | select CPU_V7 | |
153 | select CPU_V7_HAS_NONSEC | |
154 | select CPU_V7_HAS_VIRT | |
155 | select ARCH_SUPPORT_PSCI | |
156 | select SUNXI_GEN_SUN6I | |
7d06e59f IZ |
157 | select SUNXI_DRAM_DW |
158 | select SUNXI_DRAM_DW_16BIT | |
159 | select SUPPORT_SPL | |
c199489f IZ |
160 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
161 | ||
1871a8ca HG |
162 | config MACH_SUN9I |
163 | bool "sun9i (Allwinner A80)" | |
164 | select CPU_V7 | |
bc613d85 | 165 | select SUNXI_HIGH_SRAM |
1871a8ca | 166 | select SUNXI_GEN_SUN6I |
a98c296a | 167 | select SUPPORT_SPL |
1871a8ca | 168 | |
a81b7995 CYT |
169 | config MACH_SUN50I |
170 | bool "sun50i (Allwinner A64)" | |
171 | select ARM64 | |
a05a4549 | 172 | select DM_I2C |
1ae5def6 | 173 | select SUNXI_DE2 |
a81b7995 | 174 | select SUNXI_GEN_SUN6I |
bc613d85 | 175 | select SUNXI_HIGH_SRAM |
eb77f5c9 | 176 | select SUPPORT_SPL |
9934aba4 | 177 | select SUNXI_DRAM_DW |
87098d70 | 178 | select SUNXI_DRAM_DW_32BIT |
d29adf8e AP |
179 | select FIT |
180 | select SPL_LOAD_FIT | |
a81b7995 | 181 | |
997bde60 AP |
182 | config MACH_SUN50I_H5 |
183 | bool "sun50i (Allwinner H5)" | |
184 | select ARM64 | |
185 | select MACH_SUNXI_H3_H5 | |
186 | select SUNXI_HIGH_SRAM | |
d29adf8e AP |
187 | select FIT |
188 | select SPL_LOAD_FIT | |
997bde60 | 189 | |
2c7e3b90 | 190 | endchoice |
8a6564da | 191 | |
5e6bacdb HG |
192 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
193 | config MACH_SUN8I | |
194 | bool | |
301791c9 CYT |
195 | default y if MACH_SUN8I_A23 |
196 | default y if MACH_SUN8I_A33 | |
197 | default y if MACH_SUN8I_A83T | |
198 | default y if MACH_SUNXI_H3_H5 | |
379febac | 199 | default y if MACH_SUN8I_R40 |
c199489f | 200 | default y if MACH_SUN8I_V3S |
5e6bacdb | 201 | |
b5402d13 AP |
202 | config RESERVE_ALLWINNER_BOOT0_HEADER |
203 | bool "reserve space for Allwinner boot0 header" | |
204 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
205 | ---help--- | |
206 | Prepend a 1536 byte (empty) header to the U-Boot image file, to be | |
207 | filled with magic values post build. The Allwinner provided boot0 | |
208 | blob relies on this information to load and execute U-Boot. | |
209 | Only needed on 64-bit Allwinner boards so far when using boot0. | |
210 | ||
83843c9b AP |
211 | config ARM_BOOT_HOOK_RMR |
212 | bool | |
213 | depends on ARM64 | |
214 | default y | |
215 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
216 | ---help--- | |
217 | Insert some ARM32 code at the very beginning of the U-Boot binary | |
218 | which uses an RMR register write to bring the core into AArch64 mode. | |
219 | The very first instruction acts as a switch, since it's carefully | |
220 | chosen to be a NOP in one mode and a branch in the other, so the | |
221 | code would only be executed if not already in AArch64. | |
222 | This allows both the SPL and the U-Boot proper to be entered in | |
223 | either mode and switch to AArch64 if needed. | |
224 | ||
f6457ce5 IZ |
225 | if SUNXI_DRAM_DW |
226 | config SUNXI_DRAM_DDR3 | |
227 | bool | |
228 | ||
67337e68 IZ |
229 | config SUNXI_DRAM_DDR2 |
230 | bool | |
231 | ||
72cc9870 IZ |
232 | config SUNXI_DRAM_LPDDR3 |
233 | bool | |
234 | ||
f6457ce5 IZ |
235 | choice |
236 | prompt "DRAM Type and Timing" | |
3ec0698b IZ |
237 | default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S |
238 | default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S | |
f6457ce5 IZ |
239 | |
240 | config SUNXI_DRAM_DDR3_1333 | |
241 | bool "DDR3 1333" | |
242 | select SUNXI_DRAM_DDR3 | |
3ec0698b | 243 | depends on !MACH_SUN8I_V3S |
f6457ce5 IZ |
244 | ---help--- |
245 | This option is the original only supported memory type, which suits | |
246 | many H3/H5/A64 boards available now. | |
247 | ||
ec4670a1 IZ |
248 | config SUNXI_DRAM_LPDDR3_STOCK |
249 | bool "LPDDR3 with Allwinner stock configuration" | |
250 | select SUNXI_DRAM_LPDDR3 | |
251 | ---help--- | |
252 | This option is the LPDDR3 timing used by the stock boot0 by | |
253 | Allwinner. | |
254 | ||
67337e68 IZ |
255 | config SUNXI_DRAM_DDR2_V3S |
256 | bool "DDR2 found in V3s chip" | |
257 | select SUNXI_DRAM_DDR2 | |
3ec0698b | 258 | depends on MACH_SUN8I_V3S |
67337e68 IZ |
259 | ---help--- |
260 | This option is only for the DDR2 memory chip which is co-packaged in | |
261 | Allwinner V3s SoC. | |
262 | ||
f6457ce5 IZ |
263 | endchoice |
264 | endif | |
265 | ||
f5fd8caf VP |
266 | config DRAM_TYPE |
267 | int "sunxi dram type" | |
268 | depends on MACH_SUN8I_A83T | |
269 | default 3 | |
270 | ---help--- | |
271 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 272 | |
37781a1a | 273 | config DRAM_CLK |
8ffc487c | 274 | int "sunxi dram clock speed" |
297bb9e0 | 275 | default 792 if MACH_SUN9I |
fab03e30 | 276 | default 648 if MACH_SUN8I_R40 |
8ffc487c | 277 | default 312 if MACH_SUN6I || MACH_SUN8I |
7d06e59f IZ |
278 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ |
279 | MACH_SUN8I_V3S | |
52e3182b | 280 | default 672 if MACH_SUN50I |
37781a1a | 281 | ---help--- |
297bb9e0 PT |
282 | Set the dram clock speed, valid range 240 - 480 (prior to sun9i), |
283 | must be a multiple of 24. For the sun9i (A80), the tested values | |
284 | (for DDR3-1600) are 312 to 792. | |
37781a1a | 285 | |
47e3501a SS |
286 | if MACH_SUN5I || MACH_SUN7I |
287 | config DRAM_MBUS_CLK | |
288 | int "sunxi mbus clock speed" | |
289 | default 300 | |
290 | ---help--- | |
291 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
292 | ||
293 | endif | |
294 | ||
37781a1a | 295 | config DRAM_ZQ |
8ffc487c HG |
296 | int "sunxi dram zq value" |
297 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
298 | default 127 if MACH_SUN7I | |
7d06e59f | 299 | default 14779 if MACH_SUN8I_V3S |
fab03e30 | 300 | default 3881979 if MACH_SUN8I_R40 |
58b628ed | 301 | default 4145117 if MACH_SUN9I |
52e3182b | 302 | default 3881915 if MACH_SUN50I |
37781a1a | 303 | ---help--- |
e1a0888e | 304 | Set the dram zq value. |
8ffc487c | 305 | |
8975cdf4 HG |
306 | config DRAM_ODT_EN |
307 | bool "sunxi dram odt enable" | |
308 | default n if !MACH_SUN8I_A23 | |
309 | default y if MACH_SUN8I_A23 | |
fab03e30 | 310 | default y if MACH_SUN8I_R40 |
eb77f5c9 | 311 | default y if MACH_SUN50I |
8975cdf4 HG |
312 | ---help--- |
313 | Select this to enable dram odt (on die termination). | |
314 | ||
8ffc487c HG |
315 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
316 | config DRAM_EMR1 | |
317 | int "sunxi dram emr1 value" | |
318 | default 0 if MACH_SUN4I | |
319 | default 4 if MACH_SUN5I || MACH_SUN7I | |
320 | ---help--- | |
e1a0888e | 321 | Set the dram controller emr1 value. |
d133647a | 322 | |
47e3501a SS |
323 | config DRAM_TPR3 |
324 | hex "sunxi dram tpr3 value" | |
325 | default 0 | |
326 | ---help--- | |
327 | Set the dram controller tpr3 parameter. This parameter configures | |
328 | the delay on the command lane and also phase shifts, which are | |
329 | applied for sampling incoming read data. The default value 0 | |
330 | means that no phase/delay adjustments are necessary. Properly | |
331 | configuring this parameter increases reliability at high DRAM | |
332 | clock speeds. | |
333 | ||
334 | config DRAM_DQS_GATING_DELAY | |
335 | hex "sunxi dram dqs_gating_delay value" | |
336 | default 0 | |
337 | ---help--- | |
338 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
339 | encodes the DQS gating delay for each byte lane. The delay | |
340 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
341 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
342 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
343 | The default value 0 means autodetection. The results of hardware | |
344 | autodetection are not very reliable and depend on the chip | |
345 | temperature (sometimes producing different results on cold start | |
346 | and warm reboot). But the accuracy of hardware autodetection | |
347 | is usually good enough, unless running at really high DRAM | |
348 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
349 | ||
d133647a SS |
350 | choice |
351 | prompt "sunxi dram timings" | |
352 | default DRAM_TIMINGS_VENDOR_MAGIC | |
353 | ---help--- | |
354 | Select the timings of the DDR3 chips. | |
355 | ||
356 | config DRAM_TIMINGS_VENDOR_MAGIC | |
357 | bool "Magic vendor timings from Android" | |
358 | ---help--- | |
359 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
360 | ||
361 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
362 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
363 | ---help--- | |
364 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
365 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
366 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
367 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
368 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
369 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
370 | uses a bit faster timings than DDR3-1333H). | |
371 | ||
372 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
373 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
374 | ---help--- | |
375 | Use the timings of the slowest possible JEDEC speed bin for the | |
376 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
377 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
378 | ||
379 | endchoice | |
380 | ||
37781a1a HG |
381 | endif |
382 | ||
8975cdf4 HG |
383 | if MACH_SUN8I_A23 |
384 | config DRAM_ODT_CORRECTION | |
385 | int "sunxi dram odt correction value" | |
386 | default 0 | |
387 | ---help--- | |
388 | Set the dram odt correction value (range -255 - 255). In allwinner | |
389 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
390 | in the [dram] section. When bit 31 of the odt_en variable is set | |
391 | then the correction is negative. Usually the value for this is 0. | |
392 | endif | |
393 | ||
e71b422b | 394 | config SYS_CLK_FREQ |
301791c9 CYT |
395 | default 1008000000 if MACH_SUN4I |
396 | default 1008000000 if MACH_SUN5I | |
397 | default 1008000000 if MACH_SUN6I | |
e71b422b | 398 | default 912000000 if MACH_SUN7I |
301791c9 CYT |
399 | default 1008000000 if MACH_SUN8I |
400 | default 1008000000 if MACH_SUN9I | |
401 | default 816000000 if MACH_SUN50I | |
e71b422b | 402 | |
8a6564da | 403 | config SYS_CONFIG_NAME |
c3be2793 IC |
404 | default "sun4i" if MACH_SUN4I |
405 | default "sun5i" if MACH_SUN5I | |
406 | default "sun6i" if MACH_SUN6I | |
407 | default "sun7i" if MACH_SUN7I | |
408 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 409 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 410 | default "sun50i" if MACH_SUN50I |
dd84058d | 411 | |
dd84058d | 412 | config SYS_BOARD |
dd84058d MY |
413 | default "sunxi" |
414 | ||
415 | config SYS_SOC | |
dd84058d MY |
416 | default "sunxi" |
417 | ||
f0ce28e9 SS |
418 | config UART0_PORT_F |
419 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
420 | default n |
421 | ---help--- | |
422 | Repurpose the SD card slot for getting access to the UART0 serial | |
423 | console. Primarily useful only for low level u-boot debugging on | |
424 | tablets, where normal UART0 is difficult to access and requires | |
425 | device disassembly and/or soldering. As the SD card can't be used | |
426 | at the same time, the system can be only booted in the FEL mode. | |
427 | Only enable this if you really know what you are doing. | |
428 | ||
accc9e44 | 429 | config OLD_SUNXI_KERNEL_COMPAT |
ab65006b | 430 | bool "Enable workarounds for booting old kernels" |
accc9e44 HG |
431 | default n |
432 | ---help--- | |
433 | Set this to enable various workarounds for old kernels, this results in | |
434 | sub-optimal settings for newer kernels, only enable if needed. | |
435 | ||
f5fd7886 MJ |
436 | config MACPWR |
437 | string "MAC power pin" | |
438 | default "" | |
439 | help | |
440 | Set the pin used to power the MAC. This takes a string in the format | |
441 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
442 | ||
cd82113a HG |
443 | config MMC0_CD_PIN |
444 | string "Card detect pin for mmc0" | |
7b82a229 | 445 | default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I |
cd82113a HG |
446 | default "" |
447 | ---help--- | |
448 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
449 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
450 | PH1 for pin 1 of port H. | |
451 | ||
452 | config MMC1_CD_PIN | |
453 | string "Card detect pin for mmc1" | |
454 | default "" | |
455 | ---help--- | |
456 | See MMC0_CD_PIN help text. | |
457 | ||
458 | config MMC2_CD_PIN | |
459 | string "Card detect pin for mmc2" | |
460 | default "" | |
461 | ---help--- | |
462 | See MMC0_CD_PIN help text. | |
463 | ||
464 | config MMC3_CD_PIN | |
465 | string "Card detect pin for mmc3" | |
466 | default "" | |
467 | ---help--- | |
468 | See MMC0_CD_PIN help text. | |
469 | ||
8deacca9 PK |
470 | config MMC1_PINS |
471 | string "Pins for mmc1" | |
472 | default "" | |
473 | ---help--- | |
474 | Set the pins used for mmc1, when applicable. This takes a string in the | |
475 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
476 | ||
477 | config MMC2_PINS | |
478 | string "Pins for mmc2" | |
479 | default "" | |
480 | ---help--- | |
481 | See MMC1_PINS help text. | |
482 | ||
483 | config MMC3_PINS | |
484 | string "Pins for mmc3" | |
485 | default "" | |
486 | ---help--- | |
487 | See MMC1_PINS help text. | |
488 | ||
2ccfac01 HG |
489 | config MMC_SUNXI_SLOT_EXTRA |
490 | int "mmc extra slot number" | |
491 | default -1 | |
492 | ---help--- | |
493 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
494 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
495 | support for this. | |
496 | ||
2c3c3ecb HG |
497 | config INITIAL_USB_SCAN_DELAY |
498 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
499 | default 0 | |
500 | ---help--- | |
501 | Some boards have on board usb devices which need longer than the | |
502 | USB spec's 1 second to connect from board powerup. Set this config | |
503 | option to a non 0 value to add an extra delay before the first usb | |
504 | bus scan. | |
505 | ||
4458b7a6 HG |
506 | config USB0_VBUS_PIN |
507 | string "Vbus enable pin for usb0 (otg)" | |
508 | default "" | |
509 | ---help--- | |
510 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
511 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
512 | ||
52defe8f HG |
513 | config USB0_VBUS_DET |
514 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
515 | default "" |
516 | ---help--- | |
517 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
518 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
519 | ||
48c06c98 HG |
520 | config USB0_ID_DET |
521 | string "ID detect pin for usb0 (otg)" | |
522 | default "" | |
523 | ---help--- | |
524 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
525 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
526 | ||
115200ce HG |
527 | config USB1_VBUS_PIN |
528 | string "Vbus enable pin for usb1 (ehci0)" | |
529 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 530 | default "PH27" if MACH_SUN6I |
115200ce HG |
531 | ---help--- |
532 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
533 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
534 | PH1 for pin 1 of port H. | |
535 | ||
536 | config USB2_VBUS_PIN | |
537 | string "Vbus enable pin for usb2 (ehci1)" | |
538 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 539 | default "PH24" if MACH_SUN6I |
115200ce HG |
540 | ---help--- |
541 | See USB1_VBUS_PIN help text. | |
542 | ||
60fa6301 HG |
543 | config USB3_VBUS_PIN |
544 | string "Vbus enable pin for usb3 (ehci2)" | |
545 | default "" | |
546 | ---help--- | |
547 | See USB1_VBUS_PIN help text. | |
548 | ||
6c739c5d PK |
549 | config I2C0_ENABLE |
550 | bool "Enable I2C/TWI controller 0" | |
409677ec | 551 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 |
6c739c5d | 552 | default n if MACH_SUN6I || MACH_SUN8I |
0878a8a7 | 553 | select CMD_I2C |
6c739c5d PK |
554 | ---help--- |
555 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
556 | its clock and setting up the bus. This is especially useful on devices | |
557 | with slaves connected to the bus or with pins exposed through e.g. an | |
558 | expansion port/header. | |
559 | ||
560 | config I2C1_ENABLE | |
561 | bool "Enable I2C/TWI controller 1" | |
562 | default n | |
0878a8a7 | 563 | select CMD_I2C |
6c739c5d PK |
564 | ---help--- |
565 | See I2C0_ENABLE help text. | |
566 | ||
567 | config I2C2_ENABLE | |
568 | bool "Enable I2C/TWI controller 2" | |
569 | default n | |
0878a8a7 | 570 | select CMD_I2C |
6c739c5d PK |
571 | ---help--- |
572 | See I2C0_ENABLE help text. | |
573 | ||
574 | if MACH_SUN6I || MACH_SUN7I | |
575 | config I2C3_ENABLE | |
576 | bool "Enable I2C/TWI controller 3" | |
577 | default n | |
0878a8a7 | 578 | select CMD_I2C |
6c739c5d PK |
579 | ---help--- |
580 | See I2C0_ENABLE help text. | |
581 | endif | |
582 | ||
0d8382ae | 583 | if SUNXI_GEN_SUN6I |
9d082687 JW |
584 | config R_I2C_ENABLE |
585 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
586 | # This is used for the pmic on H3 |
587 | default y if SY8106A_POWER | |
0878a8a7 | 588 | select CMD_I2C |
9d082687 JW |
589 | ---help--- |
590 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 591 | endif |
9d082687 | 592 | |
6c739c5d PK |
593 | if MACH_SUN7I |
594 | config I2C4_ENABLE | |
595 | bool "Enable I2C/TWI controller 4" | |
596 | default n | |
0878a8a7 | 597 | select CMD_I2C |
6c739c5d PK |
598 | ---help--- |
599 | See I2C0_ENABLE help text. | |
600 | endif | |
601 | ||
2fcf033d | 602 | config AXP_GPIO |
ab65006b | 603 | bool "Enable support for gpio-s on axp PMICs" |
2fcf033d HG |
604 | default n |
605 | ---help--- | |
606 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
607 | ||
7f2c521f | 608 | config VIDEO |
ab65006b | 609 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
301791c9 CYT |
610 | depends on !MACH_SUN8I_A83T |
611 | depends on !MACH_SUNXI_H3_H5 | |
379febac | 612 | depends on !MACH_SUN8I_R40 |
c199489f | 613 | depends on !MACH_SUN8I_V3S |
301791c9 CYT |
614 | depends on !MACH_SUN9I |
615 | depends on !MACH_SUN50I | |
7f2c521f LV |
616 | default y |
617 | ---help--- | |
2dae800f HG |
618 | Say Y here to add support for using a cfb console on the HDMI, LCD |
619 | or VGA output found on most sunxi devices. See doc/README.video for | |
620 | info on how to select the video output and mode. | |
621 | ||
2fbf091a | 622 | config VIDEO_HDMI |
ab65006b | 623 | bool "HDMI output support" |
2fbf091a HG |
624 | depends on VIDEO && !MACH_SUN8I |
625 | default y | |
626 | ---help--- | |
627 | Say Y here to add support for outputting video over HDMI. | |
628 | ||
d9786d23 | 629 | config VIDEO_VGA |
ab65006b | 630 | bool "VGA output support" |
d9786d23 HG |
631 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
632 | default n | |
633 | ---help--- | |
634 | Say Y here to add support for outputting video over VGA. | |
635 | ||
e2bbdfb1 | 636 | config VIDEO_VGA_VIA_LCD |
ab65006b | 637 | bool "VGA via LCD controller support" |
2583d5b1 | 638 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
639 | default n |
640 | ---help--- | |
641 | Say Y here to add support for external DACs connected to the parallel | |
642 | LCD interface driving a VGA connector, such as found on the | |
643 | Olimex A13 boards. | |
644 | ||
fb75d972 | 645 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
ab65006b | 646 | bool "Force sync active high for VGA via LCD controller support" |
fb75d972 HG |
647 | depends on VIDEO_VGA_VIA_LCD |
648 | default n | |
649 | ---help--- | |
650 | Say Y here if you've a board which uses opendrain drivers for the vga | |
651 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
652 | positive edges for a stable video output, so on boards with opendrain | |
653 | drivers the sync signals must always be active high. | |
654 | ||
507e27df CYT |
655 | config VIDEO_VGA_EXTERNAL_DAC_EN |
656 | string "LCD panel power enable pin" | |
657 | depends on VIDEO_VGA_VIA_LCD | |
658 | default "" | |
659 | ---help--- | |
660 | Set the enable pin for the external VGA DAC. This takes a string in the | |
661 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
662 | ||
39920c81 | 663 | config VIDEO_COMPOSITE |
ab65006b | 664 | bool "Composite video output support" |
39920c81 HG |
665 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
666 | default n | |
667 | ---help--- | |
668 | Say Y here to add support for outputting composite video. | |
669 | ||
2dae800f HG |
670 | config VIDEO_LCD_MODE |
671 | string "LCD panel timing details" | |
672 | depends on VIDEO | |
673 | default "" | |
674 | ---help--- | |
675 | LCD panel timing details string, leave empty if there is no LCD panel. | |
676 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
677 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 678 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 679 | |
6515032e HG |
680 | config VIDEO_LCD_DCLK_PHASE |
681 | int "LCD panel display clock phase" | |
682 | depends on VIDEO | |
683 | default 1 | |
684 | ---help--- | |
685 | Select LCD panel display clock phase shift, range 0-3. | |
686 | ||
2dae800f HG |
687 | config VIDEO_LCD_POWER |
688 | string "LCD panel power enable pin" | |
689 | depends on VIDEO | |
690 | default "" | |
691 | ---help--- | |
692 | Set the power enable pin for the LCD panel. This takes a string in the | |
693 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
694 | ||
242e3d89 HG |
695 | config VIDEO_LCD_RESET |
696 | string "LCD panel reset pin" | |
697 | depends on VIDEO | |
698 | default "" | |
699 | ---help--- | |
700 | Set the reset pin for the LCD panel. This takes a string in the format | |
701 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
702 | ||
2dae800f HG |
703 | config VIDEO_LCD_BL_EN |
704 | string "LCD panel backlight enable pin" | |
705 | depends on VIDEO | |
706 | default "" | |
707 | ---help--- | |
708 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
709 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
710 | port H. | |
711 | ||
712 | config VIDEO_LCD_BL_PWM | |
713 | string "LCD panel backlight pwm pin" | |
714 | depends on VIDEO | |
715 | default "" | |
716 | ---help--- | |
717 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
718 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 719 | |
a7403ae8 HG |
720 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
721 | bool "LCD panel backlight pwm is inverted" | |
722 | depends on VIDEO | |
723 | default y | |
724 | ---help--- | |
725 | Set this if the backlight pwm output is active low. | |
726 | ||
55410089 HG |
727 | config VIDEO_LCD_PANEL_I2C |
728 | bool "LCD panel needs to be configured via i2c" | |
729 | depends on VIDEO | |
1fc42018 | 730 | default n |
0878a8a7 | 731 | select CMD_I2C |
55410089 HG |
732 | ---help--- |
733 | Say y here if the LCD panel needs to be configured via i2c. This | |
734 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
735 | ||
736 | config VIDEO_LCD_PANEL_I2C_SDA | |
737 | string "LCD panel i2c interface SDA pin" | |
738 | depends on VIDEO_LCD_PANEL_I2C | |
739 | default "PG12" | |
740 | ---help--- | |
741 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
742 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
743 | ||
744 | config VIDEO_LCD_PANEL_I2C_SCL | |
745 | string "LCD panel i2c interface SCL pin" | |
746 | depends on VIDEO_LCD_PANEL_I2C | |
747 | default "PG10" | |
748 | ---help--- | |
749 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
750 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
751 | ||
213480e1 HG |
752 | |
753 | # Note only one of these may be selected at a time! But hidden choices are | |
754 | # not supported by Kconfig | |
755 | config VIDEO_LCD_IF_PARALLEL | |
756 | bool | |
757 | ||
758 | config VIDEO_LCD_IF_LVDS | |
759 | bool | |
760 | ||
1ae5def6 JS |
761 | config SUNXI_DE2 |
762 | bool | |
763 | default n | |
764 | ||
56009451 JS |
765 | config VIDEO_DE2 |
766 | bool "Display Engine 2 video driver" | |
767 | depends on SUNXI_DE2 | |
768 | select DM_VIDEO | |
769 | select DISPLAY | |
770 | default y | |
771 | ---help--- | |
772 | Say y here if you want to build DE2 video driver which is present on | |
773 | newer SoCs. Currently only HDMI output is supported. | |
774 | ||
213480e1 HG |
775 | |
776 | choice | |
777 | prompt "LCD panel support" | |
778 | depends on VIDEO | |
779 | ---help--- | |
780 | Select which type of LCD panel to support. | |
781 | ||
782 | config VIDEO_LCD_PANEL_PARALLEL | |
783 | bool "Generic parallel interface LCD panel" | |
784 | select VIDEO_LCD_IF_PARALLEL | |
785 | ||
786 | config VIDEO_LCD_PANEL_LVDS | |
787 | bool "Generic lvds interface LCD panel" | |
788 | select VIDEO_LCD_IF_LVDS | |
789 | ||
97ece830 SS |
790 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
791 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
792 | select VIDEO_LCD_SSD2828 | |
793 | select VIDEO_LCD_IF_PARALLEL | |
794 | ---help--- | |
c1cfd519 HG |
795 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
796 | ||
797 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
798 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
799 | select VIDEO_LCD_ANX9804 | |
800 | select VIDEO_LCD_IF_PARALLEL | |
801 | select VIDEO_LCD_PANEL_I2C | |
802 | ---help--- | |
803 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
804 | connected via an ANX9804 bridge chip. | |
97ece830 | 805 | |
27515b20 HG |
806 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
807 | bool "Hitachi tx18d42vm LCD panel" | |
808 | select VIDEO_LCD_HITACHI_TX18D42VM | |
809 | select VIDEO_LCD_IF_LVDS | |
810 | ---help--- | |
811 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
812 | ||
aad2ac24 HG |
813 | config VIDEO_LCD_TL059WV5C0 |
814 | bool "tl059wv5c0 LCD panel" | |
815 | select VIDEO_LCD_PANEL_I2C | |
816 | select VIDEO_LCD_IF_PARALLEL | |
817 | ---help--- | |
818 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
819 | Aigo M60/M608/M606 tablets. | |
820 | ||
213480e1 HG |
821 | endchoice |
822 | ||
d7b560e6 MJ |
823 | config SATAPWR |
824 | string "SATA power pin" | |
825 | default "" | |
826 | help | |
827 | Set the pins used to power the SATA. This takes a string in the | |
828 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
829 | port H. | |
213480e1 | 830 | |
c13f60d9 HG |
831 | config GMAC_TX_DELAY |
832 | int "GMAC Transmit Clock Delay Chain" | |
833 | default 0 | |
834 | ---help--- | |
835 | Set the GMAC Transmit Clock Delay Chain value. | |
836 | ||
ff42d107 | 837 | config SPL_STACK_R_ADDR |
301791c9 CYT |
838 | default 0x4fe00000 if MACH_SUN4I |
839 | default 0x4fe00000 if MACH_SUN5I | |
840 | default 0x4fe00000 if MACH_SUN6I | |
841 | default 0x4fe00000 if MACH_SUN7I | |
842 | default 0x4fe00000 if MACH_SUN8I | |
ff42d107 | 843 | default 0x2fe00000 if MACH_SUN9I |
301791c9 | 844 | default 0x4fe00000 if MACH_SUN50I |
ff42d107 | 845 | |
dd84058d | 846 | endif |