[people/ms/u-boot.git] / arch / arm / mach-sunxi / board.c

/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <i2c.h>
#include <serial.h>
#include <spl.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
#include <asm/arch/mmc.h>

#include <linux/compiler.h>

struct fel_stash {
	uint32_t sp;
	uint32_t lr;
	uint32_t cpsr;
	uint32_t sctlr;
	uint32_t vbar;
	uint32_t cr;
};

struct fel_stash fel_stash __attribute__((section(".data")));

#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>

static struct mm_region sunxi_mem_map[] = {
	{
		/* SRAM, MMIO regions */
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE
	}, {
		/* RAM */
		.virt = 0x40000000UL,
		.phys = 0x40000000UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		/* List terminator */
		0,
	}
};
struct mm_region *mem_map = sunxi_mem_map;
#endif

static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
    defined(CONFIG_MACH_SUN7I) || \
    defined(CONFIG_MACH_SUN8I_R40)
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
				 defined(CONFIG_MACH_SUN7I) || \
				 defined(CONFIG_MACH_SUN8I_R40))
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif

	return 0;
}

#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
static int spl_board_load_image(struct spl_image_info *spl_image,
				struct spl_boot_device *bootdev)
{
	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	return_to_fel(fel_stash.sp, fel_stash.lr);

	return 0;
}
SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
#endif

void s_init(void)
{
	/*
	 * Undocumented magic taken from boot0, without this DRAM
	 * access gets messed up (seems cache related).
	 * The boot0 sources describe this as: "config ema for cache sram"
	 */
#if defined CONFIG_MACH_SUN6I
	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#elif defined CONFIG_MACH_SUN8I
	__maybe_unused uint version;

	/* Unlock sram version info reg, read it, relock */
	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));

	/*
	 * Ideally this would be a switch case, but we do not know exactly
	 * which versions there are and which version needs which settings,
	 * so reproduce the per SoC code from the BSP.
	 */
#if defined CONFIG_MACH_SUN8I_A23
	if (version == 0x1650)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	else /* 0x1661 ? */
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#elif defined CONFIG_MACH_SUN8I_A33
	if (version != 0x1667)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#endif
	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
#endif

#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n"
		::: "r0");
#endif
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
	/* Enable non-secure access to some peripherals */
	tzpc_init();
#endif

	clock_init();
	timer_init();
	gpio_init();
#ifndef CONFIG_DM_I2C
	i2c_init_board();
#endif
	eth_init_board();
}

#ifdef CONFIG_SPL_BUILD
DECLARE_GLOBAL_DATA_PTR;
#endif

/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 */
uint32_t sunxi_get_boot_device(void)
{
	int boot_source;

	/*
	 * When booting from the SD card or NAND memory, the "eGON.BT0"
	 * signature is expected to be found in memory at the address 0x0004
	 * (see the "mksunxiboot" tool, which generates this header).
	 *
	 * When booting in the FEL mode over USB, this signature is patched in
	 * memory and replaced with something else by the 'fel' tool. This other
	 * signature is selected in such a way, that it can't be present in a
	 * valid bootable SD card image (because the BROM would refuse to
	 * execute the SPL in this case).
	 *
	 * This checks for the signature and if it is not found returns to
	 * the FEL code in the BROM to wait and receive the main u-boot
	 * binary over USB. If it is found, it determines where SPL was
	 * read from.
	 */
	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
		return BOOT_DEVICE_BOARD;

	boot_source = readb(SPL_ADDR + 0x28);
	switch (boot_source) {
	case SUNXI_BOOTED_FROM_MMC0:
		return BOOT_DEVICE_MMC1;
	case SUNXI_BOOTED_FROM_NAND:
		return BOOT_DEVICE_NAND;
	case SUNXI_BOOTED_FROM_MMC2:
		return BOOT_DEVICE_MMC2;
	case SUNXI_BOOTED_FROM_SPI:
		return BOOT_DEVICE_SPI;
	}

	panic("Unknown boot source %d\n", boot_source);
	return -1;		/* Never reached */
}

#ifdef CONFIG_SPL_BUILD
u32 spl_boot_device(void)
{
	return sunxi_get_boot_device();
}

void board_init_f(ulong dummy)
{
	spl_init();
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();
}
#endif

void reset_cpu(ulong addr)
{
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
#elif defined(CONFIG_SUNXI_GEN_SUN6I)
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
	while (1) { }
#endif
}

#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Some init for sunxi platform.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#include <common.h>
a151403f	14	#include <mmc.h>
6620377e	15	#include <i2c.h>
cba69eee	16	#include <serial.h>
cba69eee	17	#include <spl.h>
cba69eee IC	18	#include <asm/gpio.h>
	19	#include <asm/io.h>
	20	#include <asm/arch/clock.h>
	21	#include <asm/arch/gpio.h>
af654d14	22	#include <asm/arch/spl.h>
cba69eee IC	23	#include <asm/arch/sys_proto.h>
cba69eee IC	24	#include <asm/arch/timer.h>
92369844	25	#include <asm/arch/tzpc.h>
a151403f	26	#include <asm/arch/mmc.h>
cba69eee	27
799aff38 IC	28	#include <linux/compiler.h>
799aff38 IC	29
942cb0b6 SG	30	struct fel_stash {
	31	uint32_t sp;
	32	uint32_t lr;
840fe95c SS	33	uint32_t cpsr;
	34	uint32_t sctlr;
	35	uint32_t vbar;
	36	uint32_t cr;
942cb0b6 SG	37	};
	38
	39	struct fel_stash fel_stash __attribute__((section(".data")));
	40
ce6912e1	41	#ifdef CONFIG_ARM64
d96ebc46 SS	42	#include <asm/armv8/mmu.h>
	43
	44	static struct mm_region sunxi_mem_map[] = {
	45	{
	46	/* SRAM, MMIO regions */
cd4b0c5f YS	47	.virt = 0x0UL,
cd4b0c5f YS	48	.phys = 0x0UL,
d96ebc46 SS	49	.size = 0x40000000UL,
	50	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	51	PTE_BLOCK_NON_SHARE
	52	}, {
	53	/* RAM */
cd4b0c5f YS	54	.virt = 0x40000000UL,
cd4b0c5f YS	55	.phys = 0x40000000UL,
d96ebc46 SS	56	.size = 0x80000000UL,
	57	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	58	PTE_BLOCK_INNER_SHARE
	59	}, {
	60	/* List terminator */
	61	0,
	62	}
	63	};
	64	struct mm_region *mem_map = sunxi_mem_map;
	65	#endif
	66
f630974c	67	static int gpio_init(void)
cba69eee	68	{
ff2b47f6	69	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
379febac CYT	70	#if defined(CONFIG_MACH_SUN4I) \|\| \
	71	defined(CONFIG_MACH_SUN7I) \|\| \
	72	defined(CONFIG_MACH_SUN8I_R40)
ff2b47f6 CYT	73	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	74	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	75	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
	76	#endif
379febac	77	#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
6ad8c743 CYT	78	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
6ad8c743 CYT	79	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
487b3277	80	#else
6ad8c743 CYT	81	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
6ad8c743 CYT	82	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
487b3277	83	#endif
ff2b47f6	84	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
379febac CYT	85	#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) \|\| \
	86	defined(CONFIG_MACH_SUN7I) \|\| \
	87	defined(CONFIG_MACH_SUN8I_R40))
487b3277 PK	88	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
487b3277 PK	89	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
ea520947	90	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
ed41e62f	91	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	92	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
487b3277 PK	93	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
ea520947	94	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
ed41e62f	95	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
487b3277 PK	96	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
487b3277 PK	97	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
77115397	98	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
e506889c CYT	99	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	100	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	101	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	102	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
7b82a229	103	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
1c27b7dc JK	104	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	105	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	106	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
d96ebc46 SS	107	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	108	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	109	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	110	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
d5a3357f	111	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	112	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	113	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	114	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
c199489f IZ	115	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
	116	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
	117	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
	118	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
1871a8ca HG	119	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	120	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	121	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	122	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
ed41e62f	123	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	124	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
487b3277 PK	125	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
ea520947	126	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
5cd83b11 LI	127	#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	128	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	129	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	130	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
ed41e62f	131	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
487b3277 PK	132	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
487b3277 PK	133	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
c757a50b	134	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
f84269c5 HG	135	#else
	136	#error Unsupported console port number. Please fix pin mux settings in board.c
	137	#endif
cba69eee IC	138
	139	return 0;
	140	}
	141
eb77f5c9	142	#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
2a2ee2ac SG	143	static int spl_board_load_image(struct spl_image_info *spl_image,
2a2ee2ac SG	144	struct spl_boot_device *bootdev)
942cb0b6 SG	145	{
	146	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	147	return_to_fel(fel_stash.sp, fel_stash.lr);
36afd451 NK	148
36afd451 NK	149	return 0;
942cb0b6	150	}
ebc4ef61	151	SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
97d9df0a	152	#endif
942cb0b6	153
b56f6e2b	154	void s_init(void)
f630974c	155	{
583fede8 HG	156	/*
	157	* Undocumented magic taken from boot0, without this DRAM
	158	* access gets messed up (seems cache related).
	159	* The boot0 sources describe this as: "config ema for cache sram"
	160	*/
	161	#if defined CONFIG_MACH_SUN6I
f630974c	162	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
5f8afd70 HG	163	#elif defined CONFIG_MACH_SUN8I
5f8afd70 HG	164	__maybe_unused uint version;
583fede8 HG	165
	166	/* Unlock sram version info reg, read it, relock */
	167	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
5f8afd70	168	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
583fede8 HG	169	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
583fede8 HG	170
5f8afd70 HG	171	/*
	172	* Ideally this would be a switch case, but we do not know exactly
	173	* which versions there are and which version needs which settings,
	174	* so reproduce the per SoC code from the BSP.
	175	*/
	176	#if defined CONFIG_MACH_SUN8I_A23
	177	if (version == 0x1650)
583fede8 HG	178	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	179	else /* 0x1661 ? */
	180	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
5f8afd70 HG	181	#elif defined CONFIG_MACH_SUN8I_A33
	182	if (version != 0x1667)
	183	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
	184	#endif
	185	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	186	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
f630974c	187	#endif
583fede8	188
85db5831	189	#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
f630974c SG	190	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	191	asm volatile(
	192	"mrc p15, 0, r0, c1, c0, 1\n"
	193	"orr r0, r0, #1 << 6\n"
1afd0f6f AP	194	"mcr p15, 0, r0, c1, c0, 1\n"
1afd0f6f AP	195	::: "r0");
f630974c	196	#endif
5823664f CYT	197	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I_H3
5823664f CYT	198	/* Enable non-secure access to some peripherals */
92369844 CYT	199	tzpc_init();
92369844 CYT	200	#endif
f630974c SG	201
	202	clock_init();
	203	timer_init();
	204	gpio_init();
a8f01ccf	205	#ifndef CONFIG_DM_I2C
f630974c	206	i2c_init_board();
a8f01ccf	207	#endif
fc8991c6	208	eth_init_board();
b56f6e2b	209	}
f630974c	210
b56f6e2b	211	#ifdef CONFIG_SPL_BUILD
a151403f	212	DECLARE_GLOBAL_DATA_PTR;
8829076a	213	#endif
a151403f	214
b56f6e2b HG	215	/* The sunxi internal brom will try to loader external bootloader
b56f6e2b HG	216	* from mmc0, nand flash, mmc2.
b56f6e2b	217	*/
8829076a	218	uint32_t sunxi_get_boot_device(void)
b56f6e2b	219	{
ef36d9ae HG	220	int boot_source;
ef36d9ae HG	221
840fe95c	222	/*
a151403f DK	223	* When booting from the SD card or NAND memory, the "eGON.BT0"
	224	* signature is expected to be found in memory at the address 0x0004
	225	* (see the "mksunxiboot" tool, which generates this header).
840fe95c SS	226	*
	227	* When booting in the FEL mode over USB, this signature is patched in
	228	* memory and replaced with something else by the 'fel' tool. This other
	229	* signature is selected in such a way, that it can't be present in a
	230	* valid bootable SD card image (because the BROM would refuse to
	231	* execute the SPL in this case).
	232	*
a151403f DK	233	* This checks for the signature and if it is not found returns to
	234	* the FEL code in the BROM to wait and receive the main u-boot
	235	* binary over USB. If it is found, it determines where SPL was
	236	* read from.
840fe95c	237	*/
af654d14	238	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
942cb0b6	239	return BOOT_DEVICE_BOARD;
a151403f	240
ef36d9ae HG	241	boot_source = readb(SPL_ADDR + 0x28);
	242	switch (boot_source) {
	243	case SUNXI_BOOTED_FROM_MMC0:
a151403f	244	return BOOT_DEVICE_MMC1;
ef36d9ae	245	case SUNXI_BOOTED_FROM_NAND:
a151403f	246	return BOOT_DEVICE_NAND;
ef36d9ae HG	247	case SUNXI_BOOTED_FROM_MMC2:
	248	return BOOT_DEVICE_MMC2;
	249	case SUNXI_BOOTED_FROM_SPI:
	250	return BOOT_DEVICE_SPI;
a151403f DK	251	}
a151403f DK	252
ef36d9ae	253	panic("Unknown boot source %d\n", boot_source);
a151403f	254	return -1; /* Never reached */
b56f6e2b HG	255	}
b56f6e2b HG	256
8829076a MR	257	#ifdef CONFIG_SPL_BUILD
	258	u32 spl_boot_device(void)
	259	{
	260	return sunxi_get_boot_device();
	261	}
	262
b56f6e2b HG	263	void board_init_f(ulong dummy)
b56f6e2b HG	264	{
6d0bdfdd	265	spl_init();
f630974c SG	266	preloader_console_init();
	267
	268	#ifdef CONFIG_SPL_I2C_SUPPORT
	269	/* Needed early by sunxi_board_init if PMU is enabled */
	270	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	271	#endif
	272	sunxi_board_init();
f630974c SG	273	}
	274	#endif
	275
cba69eee IC	276	void reset_cpu(ulong addr)
cba69eee IC	277	{
6c7ae2bf	278	#if defined(CONFIG_SUNXI_GEN_SUN4I) \|\| defined(CONFIG_MACH_SUN8I_R40)
c7e79dec HG	279	static const struct sunxi_wdog *wdog =
	280	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	281
	282	/* Set the watchdog for its shortest interval (.5s) and wait */
	283	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	284	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
ae5de5a1 HG	285
	286	while (1) {
	287	/* sun5i sometimes gets stuck without this */
	288	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	289	}
6c7ae2bf	290	#elif defined(CONFIG_SUNXI_GEN_SUN6I)
78c396a1 CYT	291	static const struct sunxi_wdog *wdog =
	292	((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	293
	294	/* Set the watchdog for its shortest interval (.5s) and wait */
	295	writel(WDT_CFG_RESET, &wdog->cfg);
	296	writel(WDT_MODE_EN, &wdog->mode);
	297	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
fc175434	298	while (1) { }
78c396a1	299	#endif
cba69eee IC	300	}
cba69eee IC	301
d96ebc46	302	#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
cba69eee IC	303	void enable_caches(void)
	304	{
	305	/* Enable D-cache. I-cache is already enabled in start.S */
	306	dcache_enable();
	307	}
	308	#endif