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d0edce4f | 1 | /* |
2f5dac92 | 2 | * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. |
d0edce4f | 3 | * |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
d0edce4f TW |
5 | */ |
6 | ||
7 | /* Tegra cache routines */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/io.h> | |
11 | #include <asm/arch-tegra/ap.h> | |
12 | #include <asm/arch/gp_padctrl.h> | |
13 | ||
7aaa5a60 | 14 | #ifndef CONFIG_ARM64 |
d0edce4f TW |
15 | void config_cache(void) |
16 | { | |
d0edce4f TW |
17 | u32 reg = 0; |
18 | ||
19 | /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ | |
20 | asm volatile( | |
21 | "mrc p15, 0, r0, c1, c0, 1\n" | |
22 | "orr r0, r0, #0x41\n" | |
23 | "mcr p15, 0, r0, c1, c0, 1\n"); | |
24 | ||
2f5dac92 TW |
25 | /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */ |
26 | if (tegra_get_chip() < CHIPID_TEGRA114) | |
d0edce4f | 27 | return; |
2f5dac92 | 28 | |
d0edce4f TW |
29 | /* |
30 | * Systems with an architectural L2 cache must not use the PL310. | |
31 | * Config L2CTLR here for a data RAM latency of 3 cycles. | |
32 | */ | |
33 | asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); | |
34 | reg &= ~7; | |
35 | reg |= 2; | |
36 | asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); | |
37 | } | |
7aaa5a60 | 38 | #endif |