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f29f086a | 1 | /* |
7aaa5a60 | 2 | * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. |
f29f086a | 3 | * |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
f29f086a TW |
5 | */ |
6 | ||
7 | /* Tegra SoC common clock control functions */ | |
8 | ||
9 | #include <common.h> | |
03bc3f18 SG |
10 | #include <div64.h> |
11 | #include <dm.h> | |
746dc76b | 12 | #include <errno.h> |
f29f086a TW |
13 | #include <asm/io.h> |
14 | #include <asm/arch/clock.h> | |
15 | #include <asm/arch/tegra.h> | |
73c38934 | 16 | #include <asm/arch-tegra/ap.h> |
f29f086a | 17 | #include <asm/arch-tegra/clk_rst.h> |
746dc76b | 18 | #include <asm/arch-tegra/pmc.h> |
f29f086a | 19 | #include <asm/arch-tegra/timer.h> |
f29f086a TW |
20 | |
21 | /* | |
22 | * This is our record of the current clock rate of each clock. We don't | |
23 | * fill all of these in since we are only really interested in clocks which | |
24 | * we use as parents. | |
25 | */ | |
26 | static unsigned pll_rate[CLOCK_ID_COUNT]; | |
27 | ||
28 | /* | |
29 | * The oscillator frequency is fixed to one of four set values. Based on this | |
30 | * the other clocks are set up appropriately. | |
31 | */ | |
32 | static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = { | |
33 | 13000000, | |
34 | 19200000, | |
35 | 12000000, | |
36 | 26000000, | |
3e8650c0 TW |
37 | 38400000, |
38 | 48000000, | |
f29f086a TW |
39 | }; |
40 | ||
41 | /* return 1 if a peripheral ID is in range */ | |
42 | #define clock_type_id_isvalid(id) ((id) >= 0 && \ | |
43 | (id) < CLOCK_TYPE_COUNT) | |
44 | ||
45 | char pllp_valid = 1; /* PLLP is set up correctly */ | |
46 | ||
47 | /* return 1 if a periphc_internal_id is in range */ | |
48 | #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ | |
49 | (id) < PERIPHC_COUNT) | |
50 | ||
51 | /* number of clock outputs of a PLL */ | |
52 | static const u8 pll_num_clkouts[] = { | |
53 | 1, /* PLLC */ | |
54 | 1, /* PLLM */ | |
55 | 4, /* PLLP */ | |
56 | 1, /* PLLA */ | |
57 | 0, /* PLLU */ | |
58 | 0, /* PLLD */ | |
59 | }; | |
60 | ||
61 | int clock_get_osc_bypass(void) | |
62 | { | |
63 | struct clk_rst_ctlr *clkrst = | |
64 | (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
65 | u32 reg; | |
66 | ||
67 | reg = readl(&clkrst->crc_osc_ctrl); | |
68 | return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT; | |
69 | } | |
70 | ||
71 | /* Returns a pointer to the registers of the given pll */ | |
72 | static struct clk_pll *get_pll(enum clock_id clkid) | |
73 | { | |
74 | struct clk_rst_ctlr *clkrst = | |
75 | (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
76 | ||
77 | assert(clock_id_is_pll(clkid)); | |
801b05cd | 78 | if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) { |
cd3c6769 | 79 | debug("%s: Invalid PLL %d\n", __func__, clkid); |
801b05cd SG |
80 | return NULL; |
81 | } | |
f29f086a TW |
82 | return &clkrst->crc_pll[clkid]; |
83 | } | |
84 | ||
801b05cd SG |
85 | __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) |
86 | { | |
87 | return NULL; | |
88 | } | |
89 | ||
f29f086a TW |
90 | int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, |
91 | u32 *divp, u32 *cpcon, u32 *lfcon) | |
92 | { | |
93 | struct clk_pll *pll = get_pll(clkid); | |
722e000c | 94 | struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; |
f29f086a TW |
95 | u32 data; |
96 | ||
97 | assert(clkid != CLOCK_ID_USB); | |
98 | ||
99 | /* Safety check, adds to code size but is small */ | |
100 | if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB) | |
101 | return -1; | |
102 | data = readl(&pll->pll_base); | |
722e000c TW |
103 | *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; |
104 | *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; | |
105 | *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; | |
f29f086a | 106 | data = readl(&pll->pll_misc); |
722e000c TW |
107 | /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */ |
108 | *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; | |
109 | *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask; | |
110 | ||
f29f086a TW |
111 | return 0; |
112 | } | |
113 | ||
114 | unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, | |
115 | u32 divp, u32 cpcon, u32 lfcon) | |
116 | { | |
cd3c6769 | 117 | struct clk_pll *pll = NULL; |
722e000c | 118 | struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; |
5a30cee5 | 119 | struct clk_pll_simple *simple_pll = NULL; |
801b05cd | 120 | u32 misc_data, data; |
f29f086a | 121 | |
5a30cee5 | 122 | if (clkid < (enum clock_id)TEGRA_CLK_PLLS) { |
cd3c6769 | 123 | pll = get_pll(clkid); |
5a30cee5 SG |
124 | } else { |
125 | simple_pll = clock_get_simple_pll(clkid); | |
126 | if (!simple_pll) { | |
127 | debug("%s: Uknown simple PLL %d\n", __func__, clkid); | |
128 | return 0; | |
129 | } | |
130 | } | |
cd3c6769 | 131 | |
f29f086a | 132 | /* |
722e000c TW |
133 | * pllinfo has the m/n/p and kcp/kvco mask and shift |
134 | * values for all of the PLLs used in U-Boot, with any | |
135 | * SoC differences accounted for. | |
5a30cee5 SG |
136 | * |
137 | * Preserve EN_LOCKDET, etc. | |
f29f086a | 138 | */ |
5a30cee5 SG |
139 | if (pll) |
140 | misc_data = readl(&pll->pll_misc); | |
141 | else | |
142 | misc_data = readl(&simple_pll->pll_misc); | |
143 | misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); | |
144 | misc_data |= cpcon << pllinfo->kcp_shift; | |
145 | misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift); | |
146 | misc_data |= lfcon << pllinfo->kvco_shift; | |
722e000c TW |
147 | |
148 | data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); | |
149 | data |= divp << pllinfo->p_shift; | |
150 | data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */ | |
151 | ||
801b05cd SG |
152 | if (pll) { |
153 | writel(misc_data, &pll->pll_misc); | |
154 | writel(data, &pll->pll_base); | |
155 | } else { | |
5a30cee5 SG |
156 | writel(misc_data, &simple_pll->pll_misc); |
157 | writel(data, &simple_pll->pll_base); | |
801b05cd | 158 | } |
f29f086a TW |
159 | |
160 | /* calculate the stable time */ | |
161 | return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US; | |
162 | } | |
163 | ||
164 | void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, | |
165 | unsigned divisor) | |
166 | { | |
167 | u32 *reg = get_periph_source_reg(periph_id); | |
168 | u32 value; | |
169 | ||
170 | value = readl(reg); | |
171 | ||
9cb0c6dc SW |
172 | value &= ~OUT_CLK_SOURCE_31_30_MASK; |
173 | value |= source << OUT_CLK_SOURCE_31_30_SHIFT; | |
f29f086a TW |
174 | |
175 | value &= ~OUT_CLK_DIVISOR_MASK; | |
176 | value |= divisor << OUT_CLK_DIVISOR_SHIFT; | |
177 | ||
178 | writel(value, reg); | |
179 | } | |
180 | ||
7bb6199b SG |
181 | int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, |
182 | unsigned source) | |
f29f086a TW |
183 | { |
184 | u32 *reg = get_periph_source_reg(periph_id); | |
185 | ||
7bb6199b SG |
186 | switch (mux_bits) { |
187 | case MASK_BITS_31_30: | |
188 | clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, | |
189 | source << OUT_CLK_SOURCE_31_30_SHIFT); | |
190 | break; | |
191 | ||
192 | case MASK_BITS_31_29: | |
193 | clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, | |
194 | source << OUT_CLK_SOURCE_31_29_SHIFT); | |
195 | break; | |
196 | ||
197 | case MASK_BITS_31_28: | |
198 | clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, | |
199 | source << OUT_CLK_SOURCE_31_28_SHIFT); | |
200 | break; | |
201 | ||
202 | default: | |
203 | return -1; | |
204 | } | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
d0ad8a5c SW |
209 | static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits) |
210 | { | |
211 | u32 *reg = get_periph_source_reg(periph_id); | |
212 | u32 val = readl(reg); | |
213 | ||
214 | switch (mux_bits) { | |
215 | case MASK_BITS_31_30: | |
216 | val >>= OUT_CLK_SOURCE_31_30_SHIFT; | |
217 | val &= OUT_CLK_SOURCE_31_30_MASK; | |
218 | return val; | |
219 | case MASK_BITS_31_29: | |
220 | val >>= OUT_CLK_SOURCE_31_29_SHIFT; | |
221 | val &= OUT_CLK_SOURCE_31_29_MASK; | |
222 | return val; | |
223 | case MASK_BITS_31_28: | |
224 | val >>= OUT_CLK_SOURCE_31_28_SHIFT; | |
225 | val &= OUT_CLK_SOURCE_31_28_MASK; | |
226 | return val; | |
227 | default: | |
228 | return -1; | |
229 | } | |
230 | } | |
231 | ||
7bb6199b SG |
232 | void clock_ll_set_source(enum periph_id periph_id, unsigned source) |
233 | { | |
234 | clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source); | |
f29f086a TW |
235 | } |
236 | ||
237 | /** | |
238 | * Given the parent's rate and the required rate for the children, this works | |
239 | * out the peripheral clock divider to use, in 7.1 binary format. | |
240 | * | |
241 | * @param divider_bits number of divider bits (8 or 16) | |
242 | * @param parent_rate clock rate of parent clock in Hz | |
243 | * @param rate required clock rate for this clock | |
244 | * @return divider which should be used | |
245 | */ | |
246 | static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, | |
247 | unsigned long rate) | |
248 | { | |
249 | u64 divider = parent_rate * 2; | |
250 | unsigned max_divider = 1 << divider_bits; | |
251 | ||
252 | divider += rate - 1; | |
253 | do_div(divider, rate); | |
254 | ||
255 | if ((s64)divider - 2 < 0) | |
256 | return 0; | |
257 | ||
258 | if ((s64)divider - 2 >= max_divider) | |
259 | return -1; | |
260 | ||
261 | return divider - 2; | |
262 | } | |
263 | ||
264 | int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate) | |
265 | { | |
266 | struct clk_pll *pll = get_pll(clkid); | |
267 | int data = 0, div = 0, offset = 0; | |
268 | ||
269 | if (!clock_id_is_pll(clkid)) | |
270 | return -1; | |
271 | ||
272 | if (pllout + 1 > pll_num_clkouts[clkid]) | |
273 | return -1; | |
274 | ||
275 | div = clk_get_divider(8, pll_rate[clkid], rate); | |
276 | ||
277 | if (div < 0) | |
278 | return -1; | |
279 | ||
280 | /* out2 and out4 are in the high part of the register */ | |
281 | if (pllout == PLL_OUT2 || pllout == PLL_OUT4) | |
282 | offset = 16; | |
283 | ||
284 | data = (div << PLL_OUT_RATIO_SHIFT) | | |
285 | PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN; | |
286 | clrsetbits_le32(&pll->pll_out[pllout >> 1], | |
287 | PLL_OUT_RATIO_MASK << offset, data << offset); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | /** | |
293 | * Given the parent's rate and the divider in 7.1 format, this works out the | |
294 | * resulting peripheral clock rate. | |
295 | * | |
296 | * @param parent_rate clock rate of parent clock in Hz | |
297 | * @param divider which should be used in 7.1 format | |
298 | * @return effective clock rate of peripheral | |
299 | */ | |
300 | static unsigned long get_rate_from_divider(unsigned long parent_rate, | |
301 | int divider) | |
302 | { | |
303 | u64 rate; | |
304 | ||
305 | rate = (u64)parent_rate * 2; | |
306 | do_div(rate, divider + 2); | |
307 | return rate; | |
308 | } | |
309 | ||
310 | unsigned long clock_get_periph_rate(enum periph_id periph_id, | |
311 | enum clock_id parent) | |
312 | { | |
313 | u32 *reg = get_periph_source_reg(periph_id); | |
74686766 SW |
314 | unsigned parent_rate = pll_rate[parent]; |
315 | int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT; | |
316 | ||
317 | switch (periph_id) { | |
318 | case PERIPH_ID_UART1: | |
319 | case PERIPH_ID_UART2: | |
320 | case PERIPH_ID_UART3: | |
321 | case PERIPH_ID_UART4: | |
322 | case PERIPH_ID_UART5: | |
323 | #ifdef CONFIG_TEGRA20 | |
324 | /* There's no divider for these clocks in this SoC. */ | |
325 | return parent_rate; | |
326 | #else | |
327 | /* | |
328 | * This undoes the +2 in get_rate_from_divider() which I | |
329 | * believe is incorrect. Ideally we would fix | |
330 | * get_rate_from_divider(), but... Removing the +2 from | |
331 | * get_rate_from_divider() would probably require remove the -2 | |
332 | * from the tail of clk_get_divider() since I believe that's | |
333 | * only there to invert get_rate_from_divider()'s +2. Observe | |
334 | * how find_best_divider() uses those two functions together. | |
335 | * However, doing so breaks other stuff, such as Seaboard's | |
336 | * display, likely due to clock_set_pllout()'s call to | |
337 | * clk_get_divider(). Attempting to fix that by making | |
338 | * clock_set_pllout() subtract 2 from clk_get_divider()'s | |
339 | * return value doesn't help. In summary this clock driver is | |
340 | * quite broken but I'm afraid I have no idea how to fix it | |
341 | * without completely replacing it. | |
1c6c7b6b SG |
342 | * |
343 | * Be careful to avoid a divide by zero error. | |
74686766 | 344 | */ |
1c6c7b6b SG |
345 | if (div >= 1) |
346 | div -= 2; | |
74686766 SW |
347 | break; |
348 | #endif | |
349 | default: | |
350 | break; | |
351 | } | |
f29f086a | 352 | |
74686766 | 353 | return get_rate_from_divider(parent_rate, div); |
f29f086a TW |
354 | } |
355 | ||
356 | /** | |
357 | * Find the best available 7.1 format divisor given a parent clock rate and | |
358 | * required child clock rate. This function assumes that a second-stage | |
359 | * divisor is available which can divide by powers of 2 from 1 to 256. | |
360 | * | |
361 | * @param divider_bits number of divider bits (8 or 16) | |
362 | * @param parent_rate clock rate of parent clock in Hz | |
363 | * @param rate required clock rate for this clock | |
364 | * @param extra_div value for the second-stage divisor (not set if this | |
365 | * function returns -1. | |
366 | * @return divider which should be used, or -1 if nothing is valid | |
367 | * | |
368 | */ | |
369 | static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, | |
370 | unsigned long rate, int *extra_div) | |
371 | { | |
372 | int shift; | |
373 | int best_divider = -1; | |
374 | int best_error = rate; | |
375 | ||
376 | /* try dividers from 1 to 256 and find closest match */ | |
377 | for (shift = 0; shift <= 8 && best_error > 0; shift++) { | |
378 | unsigned divided_parent = parent_rate >> shift; | |
379 | int divider = clk_get_divider(divider_bits, divided_parent, | |
380 | rate); | |
381 | unsigned effective_rate = get_rate_from_divider(divided_parent, | |
382 | divider); | |
383 | int error = rate - effective_rate; | |
384 | ||
385 | /* Given a valid divider, look for the lowest error */ | |
386 | if (divider != -1 && error < best_error) { | |
387 | best_error = error; | |
388 | *extra_div = 1 << shift; | |
389 | best_divider = divider; | |
390 | } | |
391 | } | |
392 | ||
393 | /* return what we found - *extra_div will already be set */ | |
394 | return best_divider; | |
395 | } | |
396 | ||
397 | /** | |
398 | * Adjust peripheral PLL to use the given divider and source. | |
399 | * | |
400 | * @param periph_id peripheral to adjust | |
401 | * @param source Source number (0-3 or 0-7) | |
402 | * @param mux_bits Number of mux bits (2 or 4) | |
403 | * @param divider Required divider in 7.1 or 15.1 format | |
404 | * @return 0 if ok, -1 on error (requesting a parent clock which is not valid | |
405 | * for this peripheral) | |
406 | */ | |
407 | static int adjust_periph_pll(enum periph_id periph_id, int source, | |
408 | int mux_bits, unsigned divider) | |
409 | { | |
410 | u32 *reg = get_periph_source_reg(periph_id); | |
411 | ||
412 | clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK, | |
413 | divider << OUT_CLK_DIVISOR_SHIFT); | |
414 | udelay(1); | |
415 | ||
416 | /* work out the source clock and set it */ | |
417 | if (source < 0) | |
418 | return -1; | |
c82014da | 419 | |
7bb6199b | 420 | clock_ll_set_source_bits(periph_id, mux_bits, source); |
c82014da | 421 | |
f29f086a TW |
422 | udelay(2); |
423 | return 0; | |
424 | } | |
425 | ||
d0ad8a5c SW |
426 | enum clock_id clock_get_periph_parent(enum periph_id periph_id) |
427 | { | |
428 | int err, mux_bits, divider_bits, type; | |
429 | int source; | |
430 | ||
431 | err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type); | |
432 | if (err) | |
433 | return CLOCK_ID_NONE; | |
434 | ||
435 | source = clock_ll_get_source_bits(periph_id, mux_bits); | |
436 | ||
437 | return get_periph_clock_id(periph_id, source); | |
438 | } | |
439 | ||
f29f086a TW |
440 | unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, |
441 | enum clock_id parent, unsigned rate, int *extra_div) | |
442 | { | |
443 | unsigned effective_rate; | |
444 | int mux_bits, divider_bits, source; | |
445 | int divider; | |
a51f7de1 | 446 | int xdiv = 0; |
f29f086a TW |
447 | |
448 | /* work out the source clock and set it */ | |
449 | source = get_periph_clock_source(periph_id, parent, &mux_bits, | |
450 | ÷r_bits); | |
451 | ||
a51f7de1 AM |
452 | divider = find_best_divider(divider_bits, pll_rate[parent], |
453 | rate, &xdiv); | |
f29f086a | 454 | if (extra_div) |
a51f7de1 AM |
455 | *extra_div = xdiv; |
456 | ||
f29f086a TW |
457 | assert(divider >= 0); |
458 | if (adjust_periph_pll(periph_id, source, mux_bits, divider)) | |
459 | return -1U; | |
460 | debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate, | |
461 | get_periph_source_reg(periph_id), | |
462 | readl(get_periph_source_reg(periph_id))); | |
463 | ||
464 | /* Check what we ended up with. This shouldn't matter though */ | |
465 | effective_rate = clock_get_periph_rate(periph_id, parent); | |
466 | if (extra_div) | |
467 | effective_rate /= *extra_div; | |
468 | if (rate != effective_rate) | |
469 | debug("Requested clock rate %u not honored (got %u)\n", | |
470 | rate, effective_rate); | |
471 | return effective_rate; | |
472 | } | |
473 | ||
474 | unsigned clock_start_periph_pll(enum periph_id periph_id, | |
475 | enum clock_id parent, unsigned rate) | |
476 | { | |
477 | unsigned effective_rate; | |
478 | ||
479 | reset_set_enable(periph_id, 1); | |
480 | clock_enable(periph_id); | |
481 | ||
482 | effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate, | |
483 | NULL); | |
484 | ||
485 | reset_set_enable(periph_id, 0); | |
486 | return effective_rate; | |
487 | } | |
488 | ||
489 | void clock_enable(enum periph_id clkid) | |
490 | { | |
491 | clock_set_enable(clkid, 1); | |
492 | } | |
493 | ||
494 | void clock_disable(enum periph_id clkid) | |
495 | { | |
496 | clock_set_enable(clkid, 0); | |
497 | } | |
498 | ||
499 | void reset_periph(enum periph_id periph_id, int us_delay) | |
500 | { | |
501 | /* Put peripheral into reset */ | |
502 | reset_set_enable(periph_id, 1); | |
503 | udelay(us_delay); | |
504 | ||
505 | /* Remove reset */ | |
506 | reset_set_enable(periph_id, 0); | |
507 | ||
508 | udelay(us_delay); | |
509 | } | |
510 | ||
511 | void reset_cmplx_set_enable(int cpu, int which, int reset) | |
512 | { | |
513 | struct clk_rst_ctlr *clkrst = | |
514 | (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
515 | u32 mask; | |
516 | ||
517 | /* Form the mask, which depends on the cpu chosen (2 or 4) */ | |
518 | assert(cpu >= 0 && cpu < MAX_NUM_CPU); | |
519 | mask = which << cpu; | |
520 | ||
521 | /* either enable or disable those reset for that CPU */ | |
522 | if (reset) | |
523 | writel(mask, &clkrst->crc_cpu_cmplx_set); | |
524 | else | |
525 | writel(mask, &clkrst->crc_cpu_cmplx_clr); | |
526 | } | |
527 | ||
c043c025 TR |
528 | unsigned int __weak clk_m_get_rate(unsigned int parent_rate) |
529 | { | |
530 | return parent_rate; | |
531 | } | |
532 | ||
f29f086a TW |
533 | unsigned clock_get_rate(enum clock_id clkid) |
534 | { | |
535 | struct clk_pll *pll; | |
722e000c TW |
536 | u32 base, divm; |
537 | u64 parent_rate, rate; | |
538 | struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; | |
f29f086a TW |
539 | |
540 | parent_rate = osc_freq[clock_get_osc_freq()]; | |
541 | if (clkid == CLOCK_ID_OSC) | |
542 | return parent_rate; | |
543 | ||
c043c025 TR |
544 | if (clkid == CLOCK_ID_CLK_M) |
545 | return clk_m_get_rate(parent_rate); | |
546 | ||
f29f086a | 547 | pll = get_pll(clkid); |
801b05cd SG |
548 | if (!pll) |
549 | return 0; | |
f29f086a TW |
550 | base = readl(&pll->pll_base); |
551 | ||
722e000c TW |
552 | rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); |
553 | divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; | |
554 | /* | |
555 | * PLLU uses p_mask/p_shift for VCO on all but T210, | |
556 | * T210 uses normal DIVP. Handled in pllinfo table. | |
557 | */ | |
6c7dc623 SW |
558 | #ifdef CONFIG_TEGRA210 |
559 | /* | |
560 | * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is | |
561 | * not applied. pllP_out2 does have divp applied. All other pllP_outN | |
562 | * are divided down from pllP_out0. We only support pllP_out0 in | |
563 | * U-Boot at the time of writing this comment. | |
564 | */ | |
565 | if (clkid != CLOCK_ID_PERIPH) | |
566 | #endif | |
567 | divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; | |
f29f086a TW |
568 | do_div(rate, divm); |
569 | return rate; | |
570 | } | |
571 | ||
572 | /** | |
573 | * Set the output frequency you want for each PLL clock. | |
574 | * PLL output frequencies are programmed by setting their N, M and P values. | |
575 | * The governing equations are: | |
576 | * VCO = (Fi / m) * n, Fo = VCO / (2^p) | |
577 | * where Fo is the output frequency from the PLL. | |
578 | * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) | |
579 | * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 | |
580 | * Please see Tegra TRM section 5.3 to get the detail for PLL Programming | |
581 | * | |
582 | * @param n PLL feedback divider(DIVN) | |
583 | * @param m PLL input divider(DIVN) | |
584 | * @param p post divider(DIVP) | |
585 | * @param cpcon base PLL charge pump(CPCON) | |
586 | * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot | |
62a3b7dd | 587 | * be overridden), 1 if PLL is already correct |
f29f086a TW |
588 | */ |
589 | int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) | |
590 | { | |
722e000c | 591 | u32 base_reg, misc_reg; |
f29f086a | 592 | struct clk_pll *pll; |
722e000c | 593 | struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; |
f29f086a TW |
594 | |
595 | pll = get_pll(clkid); | |
596 | ||
597 | base_reg = readl(&pll->pll_base); | |
598 | ||
599 | /* Set BYPASS, m, n and p to PLL_BASE */ | |
722e000c TW |
600 | base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); |
601 | base_reg |= m << pllinfo->m_shift; | |
f29f086a | 602 | |
722e000c TW |
603 | base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); |
604 | base_reg |= n << pllinfo->n_shift; | |
f29f086a | 605 | |
722e000c TW |
606 | base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift); |
607 | base_reg |= p << pllinfo->p_shift; | |
f29f086a TW |
608 | |
609 | if (clkid == CLOCK_ID_PERIPH) { | |
610 | /* | |
611 | * If the PLL is already set up, check that it is correct | |
612 | * and record this info for clock_verify() to check. | |
613 | */ | |
614 | if (base_reg & PLL_BASE_OVRRIDE_MASK) { | |
615 | base_reg |= PLL_ENABLE_MASK; | |
616 | if (base_reg != readl(&pll->pll_base)) | |
617 | pllp_valid = 0; | |
618 | return pllp_valid ? 1 : -1; | |
619 | } | |
620 | base_reg |= PLL_BASE_OVRRIDE_MASK; | |
621 | } | |
622 | ||
623 | base_reg |= PLL_BYPASS_MASK; | |
624 | writel(base_reg, &pll->pll_base); | |
625 | ||
722e000c | 626 | /* Set cpcon (KCP) to PLL_MISC */ |
f29f086a | 627 | misc_reg = readl(&pll->pll_misc); |
722e000c TW |
628 | misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); |
629 | misc_reg |= cpcon << pllinfo->kcp_shift; | |
f29f086a TW |
630 | writel(misc_reg, &pll->pll_misc); |
631 | ||
632 | /* Enable PLL */ | |
633 | base_reg |= PLL_ENABLE_MASK; | |
634 | writel(base_reg, &pll->pll_base); | |
635 | ||
636 | /* Disable BYPASS */ | |
637 | base_reg &= ~PLL_BYPASS_MASK; | |
638 | writel(base_reg, &pll->pll_base); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | void clock_ll_start_uart(enum periph_id periph_id) | |
644 | { | |
645 | /* Assert UART reset and enable clock */ | |
646 | reset_set_enable(periph_id, 1); | |
647 | clock_enable(periph_id); | |
648 | clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ | |
649 | ||
650 | /* wait for 2us */ | |
651 | udelay(2); | |
652 | ||
653 | /* De-assert reset to UART */ | |
654 | reset_set_enable(periph_id, 0); | |
655 | } | |
656 | ||
0f925822 | 657 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
f29f086a TW |
658 | int clock_decode_periph_id(const void *blob, int node) |
659 | { | |
660 | enum periph_id id; | |
661 | u32 cell[2]; | |
662 | int err; | |
663 | ||
664 | err = fdtdec_get_int_array(blob, node, "clocks", cell, | |
665 | ARRAY_SIZE(cell)); | |
666 | if (err) | |
667 | return -1; | |
668 | id = clk_id_to_periph_id(cell[1]); | |
669 | assert(clock_periph_id_isvalid(id)); | |
670 | return id; | |
671 | } | |
0f925822 | 672 | #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ |
f29f086a TW |
673 | |
674 | int clock_verify(void) | |
675 | { | |
676 | struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); | |
677 | u32 reg = readl(&pll->pll_base); | |
678 | ||
679 | if (!pllp_valid) { | |
680 | printf("Warning: PLLP %x is not correct\n", reg); | |
681 | return -1; | |
682 | } | |
683 | debug("PLLP %x is correct\n", reg); | |
684 | return 0; | |
685 | } | |
686 | ||
687 | void clock_init(void) | |
688 | { | |
6dbcc962 SW |
689 | int i; |
690 | ||
3e8650c0 | 691 | pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); |
f29f086a TW |
692 | pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); |
693 | pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); | |
3e8650c0 | 694 | pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); |
96e82a25 | 695 | pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); |
f29f086a | 696 | pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); |
3e8650c0 TW |
697 | pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; |
698 | pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); | |
c043c025 | 699 | pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M); |
3e8650c0 | 700 | |
f29f086a | 701 | debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); |
c043c025 | 702 | debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); |
3e8650c0 | 703 | debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); |
f29f086a TW |
704 | debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); |
705 | debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); | |
3e8650c0 | 706 | debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); |
96e82a25 | 707 | debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]); |
f29f086a | 708 | debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); |
6dbcc962 SW |
709 | |
710 | for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) { | |
711 | enum periph_id periph_id; | |
712 | enum clock_id parent; | |
713 | int source, mux_bits, divider_bits; | |
714 | ||
715 | periph_id = periph_clk_init_table[i].periph_id; | |
716 | parent = periph_clk_init_table[i].parent_clock_id; | |
717 | ||
718 | source = get_periph_clock_source(periph_id, parent, &mux_bits, | |
719 | ÷r_bits); | |
720 | clock_ll_set_source_bits(periph_id, mux_bits, source); | |
721 | } | |
f29f086a | 722 | } |
b9dd6215 JZ |
723 | |
724 | static void set_avp_clock_source(u32 src) | |
725 | { | |
726 | struct clk_rst_ctlr *clkrst = | |
727 | (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
728 | u32 val; | |
729 | ||
730 | val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | | |
731 | (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | | |
732 | (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | | |
733 | (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | | |
734 | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); | |
735 | writel(val, &clkrst->crc_sclk_brst_pol); | |
736 | udelay(3); | |
737 | } | |
738 | ||
739 | /* | |
740 | * This function is useful on Tegra30, and any later SoCs that have compatible | |
741 | * PLLP configuration registers. | |
7aaa5a60 | 742 | * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c |
b9dd6215 JZ |
743 | */ |
744 | void tegra30_set_up_pllp(void) | |
745 | { | |
746 | struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; | |
747 | u32 reg; | |
748 | ||
749 | /* | |
750 | * Based on the Tegra TRM, the system clock (which is the AVP clock) can | |
751 | * run up to 275MHz. On power on, the default sytem clock source is set | |
752 | * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to | |
753 | * 408MHz which is beyond system clock's upper limit. | |
754 | * | |
755 | * The fix is to set the system clock to CLK_M before initializing PLLP, | |
756 | * and then switch back to PLLP_OUT4, which has an appropriate divider | |
757 | * configured, after PLLP has been configured | |
758 | */ | |
759 | set_avp_clock_source(SCLK_SOURCE_CLKM); | |
760 | ||
761 | /* | |
762 | * PLLP output frequency set to 408Mhz | |
763 | * PLLC output frequency set to 228Mhz | |
764 | */ | |
765 | switch (clock_get_osc_freq()) { | |
766 | case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ | |
767 | clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); | |
768 | clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); | |
769 | break; | |
770 | ||
771 | case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */ | |
772 | clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8); | |
773 | clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8); | |
774 | break; | |
775 | ||
776 | case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ | |
777 | clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); | |
778 | clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); | |
779 | break; | |
780 | case CLOCK_OSC_FREQ_19_2: | |
781 | default: | |
782 | /* | |
783 | * These are not supported. It is too early to print a | |
784 | * message and the UART likely won't work anyway due to the | |
785 | * oscillator being wrong. | |
786 | */ | |
787 | break; | |
788 | } | |
789 | ||
790 | /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ | |
791 | ||
792 | /* OUT1, 2 */ | |
793 | /* Assert RSTN before enable */ | |
794 | reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN; | |
795 | writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); | |
796 | /* Set divisor and reenable */ | |
797 | reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | |
798 | | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS | |
799 | | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | |
800 | | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS; | |
801 | writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); | |
802 | ||
803 | /* OUT3, 4 */ | |
804 | /* Assert RSTN before enable */ | |
805 | reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN; | |
806 | writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); | |
807 | /* Set divisor and reenable */ | |
808 | reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | |
809 | | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS | |
810 | | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | |
811 | | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS; | |
812 | writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); | |
813 | ||
814 | set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4); | |
815 | } | |
746dc76b SG |
816 | |
817 | int clock_external_output(int clk_id) | |
818 | { | |
819 | struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; | |
820 | ||
821 | if (clk_id >= 1 && clk_id <= 3) { | |
822 | setbits_le32(&pmc->pmc_clk_out_cntrl, | |
823 | 1 << (2 + (clk_id - 1) * 8)); | |
824 | } else { | |
825 | printf("%s: Unknown output clock id %d\n", __func__, clk_id); | |
826 | return -EINVAL; | |
827 | } | |
828 | ||
829 | return 0; | |
830 | } | |
46864cc8 SG |
831 | |
832 | __weak bool clock_early_init_done(void) | |
833 | { | |
834 | return true; | |
835 | } |