[people/ms/u-boot.git] / arch / arm / mach-tegra / tegra20 / pinmux.c

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* Tegra20 pin multiplexing functions */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>

/*
 * This defines the order of the pin mux control bits in the registers. For
 * some reason there is no correspendence between the tristate, pin mux and
 * pullup/pulldown registers.
 */
enum pmux_ctlid {
	/* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
	MUXCTL_UAA,
	MUXCTL_UAB,
	MUXCTL_UAC,
	MUXCTL_UAD,
	MUXCTL_UDA,
	MUXCTL_RESERVED5,
	MUXCTL_ATE,
	MUXCTL_RM,

	MUXCTL_ATB,
	MUXCTL_RESERVED9,
	MUXCTL_ATD,
	MUXCTL_ATC,
	MUXCTL_ATA,
	MUXCTL_KBCF,
	MUXCTL_KBCE,
	MUXCTL_SDMMC1,

	/* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
	MUXCTL_GMA,
	MUXCTL_GMC,
	MUXCTL_HDINT,
	MUXCTL_SLXA,
	MUXCTL_OWC,
	MUXCTL_SLXC,
	MUXCTL_SLXD,
	MUXCTL_SLXK,

	MUXCTL_UCA,
	MUXCTL_UCB,
	MUXCTL_DTA,
	MUXCTL_DTB,
	MUXCTL_RESERVED28,
	MUXCTL_DTC,
	MUXCTL_DTD,
	MUXCTL_DTE,

	/* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
	MUXCTL_DDC,
	MUXCTL_CDEV1,
	MUXCTL_CDEV2,
	MUXCTL_CSUS,
	MUXCTL_I2CP,
	MUXCTL_KBCA,
	MUXCTL_KBCB,
	MUXCTL_KBCC,

	MUXCTL_IRTX,
	MUXCTL_IRRX,
	MUXCTL_DAP1,
	MUXCTL_DAP2,
	MUXCTL_DAP3,
	MUXCTL_DAP4,
	MUXCTL_GMB,
	MUXCTL_GMD,

	/* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
	MUXCTL_GME,
	MUXCTL_GPV,
	MUXCTL_GPU,
	MUXCTL_SPDO,
	MUXCTL_SPDI,
	MUXCTL_SDB,
	MUXCTL_SDC,
	MUXCTL_SDD,

	MUXCTL_SPIH,
	MUXCTL_SPIG,
	MUXCTL_SPIF,
	MUXCTL_SPIE,
	MUXCTL_SPID,
	MUXCTL_SPIC,
	MUXCTL_SPIB,
	MUXCTL_SPIA,

	/* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
	MUXCTL_LPW0,
	MUXCTL_LPW1,
	MUXCTL_LPW2,
	MUXCTL_LSDI,
	MUXCTL_LSDA,
	MUXCTL_LSPI,
	MUXCTL_LCSN,
	MUXCTL_LDC,

	MUXCTL_LSCK,
	MUXCTL_LSC0,
	MUXCTL_LSC1,
	MUXCTL_LHS,
	MUXCTL_LVS,
	MUXCTL_LM0,
	MUXCTL_LM1,
	MUXCTL_LVP0,

	/* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
	MUXCTL_LD0,
	MUXCTL_LD1,
	MUXCTL_LD2,
	MUXCTL_LD3,
	MUXCTL_LD4,
	MUXCTL_LD5,
	MUXCTL_LD6,
	MUXCTL_LD7,

	MUXCTL_LD8,
	MUXCTL_LD9,
	MUXCTL_LD10,
	MUXCTL_LD11,
	MUXCTL_LD12,
	MUXCTL_LD13,
	MUXCTL_LD14,
	MUXCTL_LD15,

	/* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
	MUXCTL_LD16,
	MUXCTL_LD17,
	MUXCTL_LHP1,
	MUXCTL_LHP2,
	MUXCTL_LVP1,
	MUXCTL_LHP0,
	MUXCTL_RESERVED102,
	MUXCTL_LPP,

	MUXCTL_LDI,
	MUXCTL_PMC,
	MUXCTL_CRTP,
	MUXCTL_PTA,
	MUXCTL_RESERVED108,
	MUXCTL_KBCD,
	MUXCTL_GPU7,
	MUXCTL_DTF,

	MUXCTL_NONE = -1,
};

/*
 * And this defines the order of the pullup/pulldown controls which are again
 * in a different order
 */
enum pmux_pullid {
	/* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
	PUCTL_ATA,
	PUCTL_ATB,
	PUCTL_ATC,
	PUCTL_ATD,
	PUCTL_ATE,
	PUCTL_DAP1,
	PUCTL_DAP2,
	PUCTL_DAP3,

	PUCTL_DAP4,
	PUCTL_DTA,
	PUCTL_DTB,
	PUCTL_DTC,
	PUCTL_DTD,
	PUCTL_DTE,
	PUCTL_DTF,
	PUCTL_GPV,

	/* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
	PUCTL_RM,
	PUCTL_I2CP,
	PUCTL_PTA,
	PUCTL_GPU7,
	PUCTL_KBCA,
	PUCTL_KBCB,
	PUCTL_KBCC,
	PUCTL_KBCD,

	PUCTL_SPDI,
	PUCTL_SPDO,
	PUCTL_GPSLXAU,
	PUCTL_CRTP,
	PUCTL_SLXC,
	PUCTL_SLXD,
	PUCTL_SLXK,

	/* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
	PUCTL_CDEV1,
	PUCTL_CDEV2,
	PUCTL_SPIA,
	PUCTL_SPIB,
	PUCTL_SPIC,
	PUCTL_SPID,
	PUCTL_SPIE,
	PUCTL_SPIF,

	PUCTL_SPIG,
	PUCTL_SPIH,
	PUCTL_IRTX,
	PUCTL_IRRX,
	PUCTL_GME,
	PUCTL_RESERVED45,
	PUCTL_XM2D,
	PUCTL_XM2C,

	/* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
	PUCTL_UAA,
	PUCTL_UAB,
	PUCTL_UAC,
	PUCTL_UAD,
	PUCTL_UCA,
	PUCTL_UCB,
	PUCTL_LD17,
	PUCTL_LD19_18,

	PUCTL_LD21_20,
	PUCTL_LD23_22,
	PUCTL_LS,
	PUCTL_LC,
	PUCTL_CSUS,
	PUCTL_DDRC,
	PUCTL_SDC,
	PUCTL_SDD,

	/* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
	PUCTL_KBCF,
	PUCTL_KBCE,
	PUCTL_PMCA,
	PUCTL_PMCB,
	PUCTL_PMCC,
	PUCTL_PMCD,
	PUCTL_PMCE,
	PUCTL_CK32,

	PUCTL_UDA,
	PUCTL_SDMMC1,
	PUCTL_GMA,
	PUCTL_GMB,
	PUCTL_GMC,
	PUCTL_GMD,
	PUCTL_DDC,
	PUCTL_OWC,

	PUCTL_NONE = -1
};

/* Convenient macro for defining pin group properties */
#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd)	\
	{						\
		.funcs = {				\
			PMUX_FUNC_ ## f0,		\
			PMUX_FUNC_ ## f1,		\
			PMUX_FUNC_ ## f2,		\
			PMUX_FUNC_ ## f3,		\
		},					\
		.ctl_id = mux,				\
		.pull_id = pupd				\
	}

/* A normal pin group where the mux name and pull-up name match */
#define PIN(pingrp, f0, f1, f2, f3) \
	PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)

/* A pin group where the pull-up name doesn't have a 1-1 mapping */
#define PINP(pingrp, f0, f1, f2, f3, pupd) \
	PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)

/* A pin group number which is not used */
#define PIN_RESERVED \
	PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)

#define DRVGRP(drvgrp) \
	PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)

static const struct pmux_pingrp_desc tegra20_pingroups[] = {
	PIN(ATA,    IDE,       NAND,      GMI,       RSVD4),
	PIN(ATB,    IDE,       NAND,      GMI,       SDIO4),
	PIN(ATC,    IDE,       NAND,      GMI,       SDIO4),
	PIN(ATD,    IDE,       NAND,      GMI,       SDIO4),
	PIN(CDEV1,  OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC),
	PIN(CDEV2,  OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4),
	PIN(CSUS,   PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
	PIN(DAP1,   DAP1,      RSVD2,     GMI,       SDIO2),

	PIN(DAP2,   DAP2,      TWC,       RSVD3,     GMI),
	PIN(DAP3,   DAP3,      RSVD2,     RSVD3,     RSVD4),
	PIN(DAP4,   DAP4,      RSVD2,     GMI,       RSVD4),
	PIN(DTA,    RSVD1,     SDIO2,     VI,        RSVD4),
	PIN(DTB,    RSVD1,     RSVD2,     VI,        SPI1),
	PIN(DTC,    RSVD1,     RSVD2,     VI,        RSVD4),
	PIN(DTD,    RSVD1,     SDIO2,     VI,        RSVD4),
	PIN(DTE,    RSVD1,     RSVD2,     VI,        SPI1),

	PINP(GPU,   PWM,       UARTA,     GMI,       RSVD4,         GPSLXAU),
	PIN(GPV,    PCIE,      RSVD2,     RSVD3,     RSVD4),
	PIN(I2CP,   I2C,       RSVD2,     RSVD3,     RSVD4),
	PIN(IRTX,   UARTA,     UARTB,     GMI,       SPI4),
	PIN(IRRX,   UARTA,     UARTB,     GMI,       SPI4),
	PIN(KBCB,   KBC,       NAND,      SDIO2,     MIO),
	PIN(KBCA,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL),
	PINP(PMC,   PWR_ON,    PWR_INTR,  RSVD3,     RSVD4,         NONE),

	PIN(PTA,    I2C2,      HDMI,      GMI,       RSVD4),
	PIN(RM,     I2C,       RSVD2,     RSVD3,     RSVD4),
	PIN(KBCE,   KBC,       NAND,      OWR,       RSVD4),
	PIN(KBCF,   KBC,       NAND,      TRACE,     MIO),
	PIN(GMA,    UARTE,     SPI3,      GMI,       SDIO4),
	PIN(GMC,    UARTD,     SPI4,      GMI,       SFLASH),
	PIN(SDMMC1, SDIO1,     RSVD2,     UARTE,     UARTA),
	PIN(OWC,    OWR,       RSVD2,     RSVD3,     RSVD4),

	PIN(GME,    RSVD1,     DAP5,      GMI,       SDIO4),
	PIN(SDC,    PWM,       TWC,       SDIO3,     SPI3),
	PIN(SDD,    UARTA,     PWM,       SDIO3,     SPI3),
	PIN_RESERVED,
	PINP(SLXA,  PCIE,      SPI4,      SDIO3,     SPI2,          CRTP),
	PIN(SLXC,   SPDIF,     SPI4,      SDIO3,     SPI2),
	PIN(SLXD,   SPDIF,     SPI4,      SDIO3,     SPI2),
	PIN(SLXK,   PCIE,      SPI4,      SDIO3,     SPI2),

	PIN(SPDI,   SPDIF,     RSVD2,     I2C,       SDIO2),
	PIN(SPDO,   SPDIF,     RSVD2,     I2C,       SDIO2),
	PIN(SPIA,   SPI1,      SPI2,      SPI3,      GMI),
	PIN(SPIB,   SPI1,      SPI2,      SPI3,      GMI),
	PIN(SPIC,   SPI1,      SPI2,      SPI3,      GMI),
	PIN(SPID,   SPI2,      SPI1,      SPI2_ALT,  GMI),
	PIN(SPIE,   SPI2,      SPI1,      SPI2_ALT,  GMI),
	PIN(SPIF,   SPI3,      SPI1,      SPI2,      RSVD4),

	PIN(SPIG,   SPI3,      SPI2,      SPI2_ALT,  I2C),
	PIN(SPIH,   SPI3,      SPI2,      SPI2_ALT,  I2C),
	PIN(UAA,    SPI3,      MIPI_HS,   UARTA,     ULPI),
	PIN(UAB,    SPI2,      MIPI_HS,   UARTA,     ULPI),
	PIN(UAC,    OWR,       RSVD2,     RSVD3,     RSVD4),
	PIN(UAD,    UARTB,     SPDIF,     UARTA,     SPI4),
	PIN(UCA,    UARTC,     RSVD2,     GMI,       RSVD4),
	PIN(UCB,    UARTC,     PWM,       GMI,       RSVD4),

	PIN_RESERVED,
	PIN(ATE,    IDE,       NAND,      GMI,       RSVD4),
	PIN(KBCC,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL),
	PIN_RESERVED,
	PIN_RESERVED,
	PIN(GMB,    IDE,       NAND,      GMI,       GMI_INT),
	PIN(GMD,    RSVD1,     NAND,      GMI,       SFLASH),
	PIN(DDC,    I2C2,      RSVD2,     RSVD3,     RSVD4),

	/* 64 */
	PINP(LD0,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD1,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD2,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD3,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD4,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD5,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD6,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD7,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),

	PINP(LD8,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD9,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD10,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD11,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD12,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD13,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD14,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD15,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),

	PINP(LD16,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
	PINP(LD17,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD17),
	PINP(LHP0,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD21_20),
	PINP(LHP1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD19_18),
	PINP(LHP2,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD19_18),
	PINP(LVP0,  DISPA,     DISPB,     RSVD3,     RSVD4,         LC),
	PINP(LVP1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD21_20),
	PINP(HDINT, HDMI,      RSVD2,     RSVD3,     RSVD4,         LC),

	PINP(LM0,   DISPA,     DISPB,     SPI3,      RSVD4,         LC),
	PINP(LM1,   DISPA,     DISPB,     RSVD3,     CRT,           LC),
	PINP(LVS,   DISPA,     DISPB,     XIO,       RSVD4,         LC),
	PINP(LSC0,  DISPA,     DISPB,     XIO,       RSVD4,         LC),
	PINP(LSC1,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
	PINP(LSCK,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
	PINP(LDC,   DISPA,     DISPB,     RSVD3,     RSVD4,         LS),
	PINP(LCSN,  DISPA,     DISPB,     SPI3,      RSVD4,         LS),

	/* 96 */
	PINP(LSPI,  DISPA,     DISPB,     XIO,       HDMI,          LC),
	PINP(LSDA,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
	PINP(LSDI,  DISPA,     DISPB,     SPI3,      RSVD4,         LS),
	PINP(LPW0,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
	PINP(LPW1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LS),
	PINP(LPW2,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
	PINP(LDI,   DISPA,     DISPB,     RSVD3,     RSVD4,         LD23_22),
	PINP(LHS,   DISPA,     DISPB,     XIO,       RSVD4,         LC),

	PINP(LPP,   DISPA,     DISPB,     RSVD3,     RSVD4,         LD23_22),
	PIN_RESERVED,
	PIN(KBCD,   KBC,       NAND,      SDIO2,     MIO),
	PIN(GPU7,   RTCK,      RSVD2,     RSVD3,     RSVD4),
	PIN(DTF,    I2C3,      RSVD2,     VI,        RSVD4),
	PIN(UDA,    SPI1,      RSVD2,     UARTD,     ULPI),
	PIN(CRTP,   CRT,       RSVD2,     RSVD3,     RSVD4),
	PINP(SDB,   UARTA,     PWM,       SDIO3,     SPI2,          NONE),

	/* these pin groups only have pullup and pull down control */
	DRVGRP(CK32),
	DRVGRP(DDRC),
	DRVGRP(PMCA),
	DRVGRP(PMCB),
	DRVGRP(PMCC),
	DRVGRP(PMCD),
	DRVGRP(PMCE),
	DRVGRP(XM2C),
	DRVGRP(XM2D),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
Commit	Line	Data
858bd095 SG	1	/*
858bd095 SG	2	* Copyright (c) 2011 The Chromium OS Authors.
858bd095	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
858bd095 SG	5	*/
858bd095 SG	6
00a2749d	7	/* Tegra20 pin multiplexing functions */
858bd095	8
150c2493	9	#include <common.h>
858bd095	10	#include <asm/io.h>
858bd095	11	#include <asm/arch/pinmux.h>
858bd095	12
20e18e05 SG	13	/*
	14	* This defines the order of the pin mux control bits in the registers. For
	15	* some reason there is no correspendence between the tristate, pin mux and
	16	* pullup/pulldown registers.
	17	*/
	18	enum pmux_ctlid {
	19	/* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
	20	MUXCTL_UAA,
	21	MUXCTL_UAB,
	22	MUXCTL_UAC,
	23	MUXCTL_UAD,
	24	MUXCTL_UDA,
	25	MUXCTL_RESERVED5,
	26	MUXCTL_ATE,
	27	MUXCTL_RM,
	28
	29	MUXCTL_ATB,
	30	MUXCTL_RESERVED9,
	31	MUXCTL_ATD,
	32	MUXCTL_ATC,
	33	MUXCTL_ATA,
	34	MUXCTL_KBCF,
	35	MUXCTL_KBCE,
	36	MUXCTL_SDMMC1,
	37
	38	/* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
	39	MUXCTL_GMA,
	40	MUXCTL_GMC,
	41	MUXCTL_HDINT,
	42	MUXCTL_SLXA,
	43	MUXCTL_OWC,
	44	MUXCTL_SLXC,
	45	MUXCTL_SLXD,
	46	MUXCTL_SLXK,
	47
	48	MUXCTL_UCA,
	49	MUXCTL_UCB,
	50	MUXCTL_DTA,
	51	MUXCTL_DTB,
	52	MUXCTL_RESERVED28,
	53	MUXCTL_DTC,
	54	MUXCTL_DTD,
	55	MUXCTL_DTE,
	56
	57	/* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
	58	MUXCTL_DDC,
	59	MUXCTL_CDEV1,
	60	MUXCTL_CDEV2,
	61	MUXCTL_CSUS,
	62	MUXCTL_I2CP,
	63	MUXCTL_KBCA,
	64	MUXCTL_KBCB,
	65	MUXCTL_KBCC,
	66
	67	MUXCTL_IRTX,
	68	MUXCTL_IRRX,
	69	MUXCTL_DAP1,
	70	MUXCTL_DAP2,
	71	MUXCTL_DAP3,
	72	MUXCTL_DAP4,
	73	MUXCTL_GMB,
	74	MUXCTL_GMD,
	75
	76	/* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
77	MUXCTL_GME,
78	MUXCTL_GPV,
79	MUXCTL_GPU,
80	MUXCTL_SPDO,
81	MUXCTL_SPDI,
82	MUXCTL_SDB,
83	MUXCTL_SDC,
84	MUXCTL_SDD,
85
86	MUXCTL_SPIH,
87	MUXCTL_SPIG,
88	MUXCTL_SPIF,
89	MUXCTL_SPIE,
90	MUXCTL_SPID,
91	MUXCTL_SPIC,
92	MUXCTL_SPIB,
93	MUXCTL_SPIA,
94
95	/* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
96	MUXCTL_LPW0,
97	MUXCTL_LPW1,
98	MUXCTL_LPW2,
99	MUXCTL_LSDI,
100	MUXCTL_LSDA,
101	MUXCTL_LSPI,
102	MUXCTL_LCSN,
103	MUXCTL_LDC,
104
105	MUXCTL_LSCK,
106	MUXCTL_LSC0,
107	MUXCTL_LSC1,
108	MUXCTL_LHS,
109	MUXCTL_LVS,
110	MUXCTL_LM0,
111	MUXCTL_LM1,
112	MUXCTL_LVP0,
113
114	/* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
115	MUXCTL_LD0,
116	MUXCTL_LD1,
117	MUXCTL_LD2,
118	MUXCTL_LD3,
119	MUXCTL_LD4,
120	MUXCTL_LD5,
121	MUXCTL_LD6,
122	MUXCTL_LD7,
123
124	MUXCTL_LD8,
125	MUXCTL_LD9,
126	MUXCTL_LD10,
127	MUXCTL_LD11,
128	MUXCTL_LD12,
129	MUXCTL_LD13,
130	MUXCTL_LD14,
131	MUXCTL_LD15,
132
133	/* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
134	MUXCTL_LD16,
135	MUXCTL_LD17,
136	MUXCTL_LHP1,
137	MUXCTL_LHP2,
138	MUXCTL_LVP1,
139	MUXCTL_LHP0,
140	MUXCTL_RESERVED102,
141	MUXCTL_LPP,
142
143	MUXCTL_LDI,
144	MUXCTL_PMC,
145	MUXCTL_CRTP,
146	MUXCTL_PTA,
147	MUXCTL_RESERVED108,
148	MUXCTL_KBCD,
149	MUXCTL_GPU7,
150	MUXCTL_DTF,
151
152	MUXCTL_NONE = -1,
153	};
154
155	/*
156	* And this defines the order of the pullup/pulldown controls which are again
157	* in a different order
158	*/
159	enum pmux_pullid {
160	/* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
161	PUCTL_ATA,
162	PUCTL_ATB,
163	PUCTL_ATC,
164	PUCTL_ATD,
165	PUCTL_ATE,
166	PUCTL_DAP1,
167	PUCTL_DAP2,
168	PUCTL_DAP3,
169
170	PUCTL_DAP4,
171	PUCTL_DTA,
172	PUCTL_DTB,
173	PUCTL_DTC,
174	PUCTL_DTD,
175	PUCTL_DTE,
176	PUCTL_DTF,
177	PUCTL_GPV,
178
179	/* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
180	PUCTL_RM,
181	PUCTL_I2CP,
182	PUCTL_PTA,
183	PUCTL_GPU7,
184	PUCTL_KBCA,
185	PUCTL_KBCB,
186	PUCTL_KBCC,
187	PUCTL_KBCD,
188
189	PUCTL_SPDI,
190	PUCTL_SPDO,
191	PUCTL_GPSLXAU,
192	PUCTL_CRTP,
193	PUCTL_SLXC,
194	PUCTL_SLXD,
195	PUCTL_SLXK,
196
197	/* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
198	PUCTL_CDEV1,
199	PUCTL_CDEV2,
200	PUCTL_SPIA,
201	PUCTL_SPIB,
202	PUCTL_SPIC,
203	PUCTL_SPID,
204	PUCTL_SPIE,
205	PUCTL_SPIF,
206
207	PUCTL_SPIG,
208	PUCTL_SPIH,
209	PUCTL_IRTX,
210	PUCTL_IRRX,
211	PUCTL_GME,
212	PUCTL_RESERVED45,
213	PUCTL_XM2D,
214	PUCTL_XM2C,
215
216	/* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
217	PUCTL_UAA,
218	PUCTL_UAB,
219	PUCTL_UAC,
220	PUCTL_UAD,
221	PUCTL_UCA,
222	PUCTL_UCB,
223	PUCTL_LD17,
224	PUCTL_LD19_18,
225
226	PUCTL_LD21_20,
227	PUCTL_LD23_22,
228	PUCTL_LS,
229	PUCTL_LC,
230	PUCTL_CSUS,
231	PUCTL_DDRC,
232	PUCTL_SDC,
233	PUCTL_SDD,
234
235	/* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
236	PUCTL_KBCF,
237	PUCTL_KBCE,
238	PUCTL_PMCA,
239	PUCTL_PMCB,
240	PUCTL_PMCC,
241	PUCTL_PMCD,
242	PUCTL_PMCE,
243	PUCTL_CK32,
244
245	PUCTL_UDA,
246	PUCTL_SDMMC1,
247	PUCTL_GMA,
248	PUCTL_GMB,
249	PUCTL_GMC,
250	PUCTL_GMD,
251	PUCTL_DDC,
252	PUCTL_OWC,
253
254	PUCTL_NONE = -1
255	};
256
20e18e05	257	/* Convenient macro for defining pin group properties */
70ad375e	258	#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
20e18e05	259	{ \
20e18e05	260	.funcs = { \
70ad375e SW	261	PMUX_FUNC_ ## f0, \
	262	PMUX_FUNC_ ## f1, \
	263	PMUX_FUNC_ ## f2, \
	264	PMUX_FUNC_ ## f3, \
20e18e05	265	}, \
20e18e05 SG	266	.ctl_id = mux, \
	267	.pull_id = pupd \
	268	}
	269
	270	/* A normal pin group where the mux name and pull-up name match */
70ad375e SW	271	#define PIN(pingrp, f0, f1, f2, f3) \
70ad375e SW	272	PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
20e18e05 SG	273
20e18e05 SG	274	/* A pin group where the pull-up name doesn't have a 1-1 mapping */
70ad375e SW	275	#define PINP(pingrp, f0, f1, f2, f3, pupd) \
70ad375e SW	276	PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
20e18e05 SG	277
	278	/* A pin group number which is not used */
	279	#define PIN_RESERVED \
70ad375e	280	PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
6ac1e542	281
70ad375e SW	282	#define DRVGRP(drvgrp) \
70ad375e SW	283	PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
20e18e05	284
dfb42fc9	285	static const struct pmux_pingrp_desc tegra20_pingroups[] = {
70ad375e SW	286	PIN(ATA, IDE, NAND, GMI, RSVD4),
	287	PIN(ATB, IDE, NAND, GMI, SDIO4),
	288	PIN(ATC, IDE, NAND, GMI, SDIO4),
	289	PIN(ATD, IDE, NAND, GMI, SDIO4),
	290	PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
	291	PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
	292	PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
	293	PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
	294
	295	PIN(DAP2, DAP2, TWC, RSVD3, GMI),
	296	PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
	297	PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
	298	PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
	299	PIN(DTB, RSVD1, RSVD2, VI, SPI1),
	300	PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
	301	PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
	302	PIN(DTE, RSVD1, RSVD2, VI, SPI1),
	303
	304	PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
	305	PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
	306	PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
	307	PIN(IRTX, UARTA, UARTB, GMI, SPI4),
	308	PIN(IRRX, UARTA, UARTB, GMI, SPI4),
	309	PIN(KBCB, KBC, NAND, SDIO2, MIO),
	310	PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
	311	PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
	312
	313	PIN(PTA, I2C2, HDMI, GMI, RSVD4),
	314	PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
	315	PIN(KBCE, KBC, NAND, OWR, RSVD4),
	316	PIN(KBCF, KBC, NAND, TRACE, MIO),
	317	PIN(GMA, UARTE, SPI3, GMI, SDIO4),
	318	PIN(GMC, UARTD, SPI4, GMI, SFLASH),
	319	PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
	320	PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
	321
	322	PIN(GME, RSVD1, DAP5, GMI, SDIO4),
	323	PIN(SDC, PWM, TWC, SDIO3, SPI3),
	324	PIN(SDD, UARTA, PWM, SDIO3, SPI3),
20e18e05	325	PIN_RESERVED,
70ad375e SW	326	PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
	327	PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
	328	PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
	329	PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
	330
	331	PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
	332	PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
	333	PIN(SPIA, SPI1, SPI2, SPI3, GMI),
	334	PIN(SPIB, SPI1, SPI2, SPI3, GMI),
	335	PIN(SPIC, SPI1, SPI2, SPI3, GMI),
	336	PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
	337	PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
	338	PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
	339
	340	PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
	341	PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
	342	PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
	343	PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
	344	PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
	345	PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
	346	PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
	347	PIN(UCB, UARTC, PWM, GMI, RSVD4),
20e18e05 SG	348
20e18e05 SG	349	PIN_RESERVED,
70ad375e SW	350	PIN(ATE, IDE, NAND, GMI, RSVD4),
70ad375e SW	351	PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
20e18e05 SG	352	PIN_RESERVED,
20e18e05 SG	353	PIN_RESERVED,
70ad375e SW	354	PIN(GMB, IDE, NAND, GMI, GMI_INT),
	355	PIN(GMD, RSVD1, NAND, GMI, SFLASH),
	356	PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
20e18e05 SG	357
20e18e05 SG	358	/* 64 */
70ad375e SW	359	PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
	360	PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
	361	PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
	362	PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
	363	PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
	364	PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
	365	PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
	366	PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
	367
	368	PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
	369	PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
	370	PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
	371	PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
	372	PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
	373	PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
	374	PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
	375	PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
	376
	377	PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
	378	PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
	379	PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
	380	PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
	381	PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
	382	PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
	383	PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
	384	PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
	385
	386	PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
	387	PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
	388	PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
	389	PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
	390	PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
	391	PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
	392	PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
	393	PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
20e18e05 SG	394
20e18e05 SG	395	/* 96 */
70ad375e SW	396	PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
	397	PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
	398	PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
	399	PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
	400	PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
	401	PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
	402	PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
	403	PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
	404
	405	PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
20e18e05	406	PIN_RESERVED,
70ad375e SW	407	PIN(KBCD, KBC, NAND, SDIO2, MIO),
	408	PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
	409	PIN(DTF, I2C3, RSVD2, VI, RSVD4),
	410	PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
	411	PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
	412	PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
20e18e05 SG	413
20e18e05 SG	414	/* these pin groups only have pullup and pull down control */
70ad375e SW	415	DRVGRP(CK32),
	416	DRVGRP(DDRC),
	417	DRVGRP(PMCA),
	418	DRVGRP(PMCB),
	419	DRVGRP(PMCC),
	420	DRVGRP(PMCD),
	421	DRVGRP(PMCE),
	422	DRVGRP(XM2C),
	423	DRVGRP(XM2D),
20e18e05	424	};
dfb42fc9	425	const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;