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b2871037 TW |
1 | /* |
2 | * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
b2871037 TW |
5 | */ |
6 | ||
7 | /* Tegra30 high-level function multiplexing */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/arch/clock.h> | |
11 | #include <asm/arch/funcmux.h> | |
12 | #include <asm/arch/pinmux.h> | |
13 | ||
14 | int funcmux_select(enum periph_id id, int config) | |
15 | { | |
16 | int bad_config = config != FUNCMUX_DEFAULT; | |
17 | ||
18 | switch (id) { | |
19 | case PERIPH_ID_UART1: | |
20 | switch (config) { | |
21 | case FUNCMUX_UART1_ULPI: | |
803d01ed SW |
22 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1, |
23 | PMUX_FUNC_UARTA); | |
24 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2, | |
25 | PMUX_FUNC_UARTA); | |
26 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3, | |
27 | PMUX_FUNC_UARTA); | |
28 | pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4, | |
29 | PMUX_FUNC_UARTA); | |
30 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1); | |
31 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2); | |
32 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3); | |
33 | pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4); | |
b2871037 TW |
34 | break; |
35 | } | |
36 | break; | |
37 | ||
38 | /* Add other periph IDs here as needed */ | |
39 | ||
40 | default: | |
41 | debug("%s: invalid periph_id %d", __func__, id); | |
42 | return -1; | |
43 | } | |
44 | ||
45 | if (bad_config) { | |
46 | debug("%s: invalid config %d for periph_id %d", __func__, | |
47 | config, id); | |
48 | return -1; | |
49 | } | |
50 | return 0; | |
51 | } |