[people/ms/u-boot.git] / arch / arm / mach-tegra / xusb-padctl-common.c

/*
 * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt

#include <common.h>
#include <errno.h>

#include "xusb-padctl-common.h"

#include <asm/arch/clock.h>

int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
{
	if (phy && phy->ops && phy->ops->prepare)
		return phy->ops->prepare(phy);

	return phy ? -ENOSYS : -EINVAL;
}

int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
{
	if (phy && phy->ops && phy->ops->enable)
		return phy->ops->enable(phy);

	return phy ? -ENOSYS : -EINVAL;
}

int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
{
	if (phy && phy->ops && phy->ops->disable)
		return phy->ops->disable(phy);

	return phy ? -ENOSYS : -EINVAL;
}

int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
{
	if (phy && phy->ops && phy->ops->unprepare)
		return phy->ops->unprepare(phy);

	return phy ? -ENOSYS : -EINVAL;
}

struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
{
	struct tegra_xusb_phy *phy;
	int i;

	for (i = 0; i < padctl.socdata->num_phys; i++) {
		phy = &padctl.socdata->phys[i];
		if (phy->type != type)
			continue;
		return phy;
	}

	return NULL;
}

static const struct tegra_xusb_padctl_lane *
tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
{
	unsigned int i;

	for (i = 0; i < padctl->socdata->num_lanes; i++)
		if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
			return &padctl->socdata->lanes[i];

	return NULL;
}

static int
tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
				 struct tegra_xusb_padctl_group *group,
				 ofnode node)
{
	unsigned int i;
	int len, ret;

	group->name = ofnode_get_name(node);

	len = ofnode_read_string_count(node, "nvidia,lanes");
	if (len < 0) {
		pr_err("failed to parse \"nvidia,lanes\" property");
		return -EINVAL;
	}

	group->num_pins = len;

	for (i = 0; i < group->num_pins; i++) {
		ret = ofnode_read_string_index(node, "nvidia,lanes", i,
					       &group->pins[i]);
		if (ret) {
			pr_err("failed to read string from \"nvidia,lanes\" property");
			return -EINVAL;
		}
	}

	group->num_pins = len;

	ret = ofnode_read_string_index(node, "nvidia,function", 0,
				       &group->func);
	if (ret) {
		pr_err("failed to parse \"nvidia,func\" property");
		return -EINVAL;
	}

	group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);

	return 0;
}

static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
					   const char *name)
{
	unsigned int i;

	for (i = 0; i < padctl->socdata->num_functions; i++)
		if (strcmp(name, padctl->socdata->functions[i]) == 0)
			return i;

	return -ENOENT;
}

static int
tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
				     const struct tegra_xusb_padctl_lane *lane,
				     const char *name)
{
	unsigned int i;
	int func;

	func = tegra_xusb_padctl_find_function(padctl, name);
	if (func < 0)
		return func;

	for (i = 0; i < lane->num_funcs; i++)
		if (lane->funcs[i] == func)
			return i;

	return -ENOENT;
}

static int
tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
			      const struct tegra_xusb_padctl_group *group)
{
	unsigned int i;

	for (i = 0; i < group->num_pins; i++) {
		const struct tegra_xusb_padctl_lane *lane;
		unsigned int func;
		u32 value;

		lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
		if (!lane) {
			pr_err("no lane for pin %s", group->pins[i]);
			continue;
		}

		func = tegra_xusb_padctl_lane_find_function(padctl, lane,
							    group->func);
		if (func < 0) {
			pr_err("function %s invalid for lane %s: %d",
			      group->func, lane->name, func);
			continue;
		}

		value = padctl_readl(padctl, lane->offset);

		/* set pin function */
		value &= ~(lane->mask << lane->shift);
		value |= func << lane->shift;

		/*
		 * Set IDDQ if supported on the lane and specified in the
		 * configuration.
		 */
		if (lane->iddq > 0 && group->iddq >= 0) {
			if (group->iddq != 0)
				value &= ~(1 << lane->iddq);
			else
				value |= 1 << lane->iddq;
		}

		padctl_writel(padctl, value, lane->offset);
	}

	return 0;
}

static int
tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
			       struct tegra_xusb_padctl_config *config)
{
	unsigned int i;

	for (i = 0; i < config->num_groups; i++) {
		const struct tegra_xusb_padctl_group *group;
		int err;

		group = &config->groups[i];

		err = tegra_xusb_padctl_group_apply(padctl, group);
		if (err < 0) {
			pr_err("failed to apply group %s: %d",
			      group->name, err);
			continue;
		}
	}

	return 0;
}

static int
tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
				  struct tegra_xusb_padctl_config *config,
				  ofnode node)
{
	ofnode subnode;

	config->name = ofnode_get_name(node);

	ofnode_for_each_subnode(subnode, node) {
		struct tegra_xusb_padctl_group *group;
		int err;

		group = &config->groups[config->num_groups];

		err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
		if (err < 0) {
			pr_err("failed to parse group %s", group->name);
			return err;
		}

		config->num_groups++;
	}

	return 0;
}

static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
				      ofnode node)
{
	ofnode subnode;
	int err;

	err = ofnode_read_resource(node, 0, &padctl->regs);
	if (err < 0) {
		pr_err("registers not found");
		return err;
	}

	ofnode_for_each_subnode(subnode, node) {
		struct tegra_xusb_padctl_config *config = &padctl->config;

		debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
		err = tegra_xusb_padctl_config_parse_dt(padctl, config,
							subnode);
		if (err < 0) {
			pr_err("failed to parse entry %s: %d",
			      config->name, err);
			continue;
		}
	}
	debug("%s: done\n", __func__);

	return 0;
}

struct tegra_xusb_padctl padctl;

int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
			     const struct tegra_xusb_padctl_soc *socdata)
{
	unsigned int i;
	int err;

	debug("%s: count=%d\n", __func__, count);
	for (i = 0; i < count; i++) {
		debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
		if (!ofnode_is_available(nodes[i]))
			continue;

		padctl.socdata = socdata;

		err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
		if (err < 0) {
			pr_err("failed to parse DT: %d", err);
			continue;
		}

		/* deassert XUSB padctl reset */
		reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);

		err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
		if (err < 0) {
			pr_err("failed to apply pinmux: %d", err);
			continue;
		}

		/* only a single instance is supported */
		break;
	}
	debug("%s: done\n", __func__);

	return 0;
}
Commit	Line	Data
1680d7b6 SW	1	/*
	2	* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
	7	#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
	8
	9	#include <common.h>
	10	#include <errno.h>
	11
	12	#include "xusb-padctl-common.h"
	13
	14	#include <asm/arch/clock.h>
	15
	16	int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
	17	{
	18	if (phy && phy->ops && phy->ops->prepare)
	19	return phy->ops->prepare(phy);
	20
	21	return phy ? -ENOSYS : -EINVAL;
	22	}
	23
	24	int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
	25	{
	26	if (phy && phy->ops && phy->ops->enable)
	27	return phy->ops->enable(phy);
	28
	29	return phy ? -ENOSYS : -EINVAL;
	30	}
	31
	32	int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
	33	{
	34	if (phy && phy->ops && phy->ops->disable)
	35	return phy->ops->disable(phy);
	36
	37	return phy ? -ENOSYS : -EINVAL;
	38	}
	39
	40	int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
	41	{
	42	if (phy && phy->ops && phy->ops->unprepare)
	43	return phy->ops->unprepare(phy);
	44
	45	return phy ? -ENOSYS : -EINVAL;
	46	}
	47
	48	struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
	49	{
	50	struct tegra_xusb_phy *phy;
	51	int i;
	52
	53	for (i = 0; i < padctl.socdata->num_phys; i++) {
	54	phy = &padctl.socdata->phys[i];
	55	if (phy->type != type)
	56	continue;
	57	return phy;
	58	}
	59
	60	return NULL;
	61	}
	62
	63	static const struct tegra_xusb_padctl_lane *
	64	tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl padctl, const char name)
65	{
66	unsigned int i;
67
68	for (i = 0; i < padctl->socdata->num_lanes; i++)
69	if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
70	return &padctl->socdata->lanes[i];
71
72	return NULL;
73	}
74
75	static int
76	tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
77	struct tegra_xusb_padctl_group *group,
be789092	78	ofnode node)
1680d7b6 SW	79	{
1680d7b6 SW	80	unsigned int i;
be789092	81	int len, ret;
1680d7b6	82
be789092	83	group->name = ofnode_get_name(node);
1680d7b6	84
be789092	85	len = ofnode_read_string_count(node, "nvidia,lanes");
1680d7b6	86	if (len < 0) {
9b643e31	87	pr_err("failed to parse \"nvidia,lanes\" property");
1680d7b6 SW	88	return -EINVAL;
	89	}
	90
	91	group->num_pins = len;
	92
	93	for (i = 0; i < group->num_pins; i++) {
be789092 SG	94	ret = ofnode_read_string_index(node, "nvidia,lanes", i,
	95	&group->pins[i]);
	96	if (ret) {
9b643e31	97	pr_err("failed to read string from \"nvidia,lanes\" property");
1680d7b6 SW	98	return -EINVAL;
	99	}
	100	}
	101
	102	group->num_pins = len;
	103
be789092 SG	104	ret = ofnode_read_string_index(node, "nvidia,function", 0,
	105	&group->func);
	106	if (ret) {
9b643e31	107	pr_err("failed to parse \"nvidia,func\" property");
1680d7b6 SW	108	return -EINVAL;
	109	}
	110
be789092	111	group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
1680d7b6 SW	112
	113	return 0;
	114	}
	115
	116	static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
	117	const char *name)
	118	{
	119	unsigned int i;
	120
	121	for (i = 0; i < padctl->socdata->num_functions; i++)
	122	if (strcmp(name, padctl->socdata->functions[i]) == 0)
	123	return i;
	124
	125	return -ENOENT;
	126	}
	127
	128	static int
	129	tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
	130	const struct tegra_xusb_padctl_lane *lane,
	131	const char *name)
	132	{
	133	unsigned int i;
	134	int func;
	135
	136	func = tegra_xusb_padctl_find_function(padctl, name);
	137	if (func < 0)
	138	return func;
	139
	140	for (i = 0; i < lane->num_funcs; i++)
	141	if (lane->funcs[i] == func)
	142	return i;
	143
	144	return -ENOENT;
	145	}
	146
	147	static int
	148	tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
	149	const struct tegra_xusb_padctl_group *group)
	150	{
	151	unsigned int i;
	152
	153	for (i = 0; i < group->num_pins; i++) {
	154	const struct tegra_xusb_padctl_lane *lane;
	155	unsigned int func;
	156	u32 value;
	157
	158	lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
	159	if (!lane) {
9b643e31	160	pr_err("no lane for pin %s", group->pins[i]);
1680d7b6 SW	161	continue;
	162	}
	163
	164	func = tegra_xusb_padctl_lane_find_function(padctl, lane,
	165	group->func);
	166	if (func < 0) {
9b643e31	167	pr_err("function %s invalid for lane %s: %d",
1680d7b6 SW	168	group->func, lane->name, func);
	169	continue;
	170	}
	171
	172	value = padctl_readl(padctl, lane->offset);
	173
	174	/* set pin function */
	175	value &= ~(lane->mask << lane->shift);
	176	value \|= func << lane->shift;
	177
	178	/*
	179	* Set IDDQ if supported on the lane and specified in the
	180	* configuration.
	181	*/
	182	if (lane->iddq > 0 && group->iddq >= 0) {
	183	if (group->iddq != 0)
	184	value &= ~(1 << lane->iddq);
	185	else
	186	value \|= 1 << lane->iddq;
	187	}
	188
	189	padctl_writel(padctl, value, lane->offset);
	190	}
	191
	192	return 0;
	193	}
	194
	195	static int
	196	tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
	197	struct tegra_xusb_padctl_config *config)
	198	{
	199	unsigned int i;
	200
	201	for (i = 0; i < config->num_groups; i++) {
	202	const struct tegra_xusb_padctl_group *group;
	203	int err;
	204
	205	group = &config->groups[i];
	206
	207	err = tegra_xusb_padctl_group_apply(padctl, group);
	208	if (err < 0) {
9b643e31	209	pr_err("failed to apply group %s: %d",
1680d7b6 SW	210	group->name, err);
	211	continue;
	212	}
	213	}
	214
	215	return 0;
	216	}
	217
	218	static int
	219	tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
	220	struct tegra_xusb_padctl_config *config,
be789092	221	ofnode node)
1680d7b6	222	{
be789092	223	ofnode subnode;
1680d7b6	224
be789092	225	config->name = ofnode_get_name(node);
1680d7b6	226
3991f42e	227	ofnode_for_each_subnode(subnode, node) {
1680d7b6 SW	228	struct tegra_xusb_padctl_group *group;
	229	int err;
	230
	231	group = &config->groups[config->num_groups];
	232
be789092	233	err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
1680d7b6	234	if (err < 0) {
9b643e31	235	pr_err("failed to parse group %s", group->name);
1680d7b6 SW	236	return err;
	237	}
	238
	239	config->num_groups++;
	240	}
	241
	242	return 0;
	243	}
	244
	245	static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
be789092	246	ofnode node)
1680d7b6	247	{
be789092 SG	248	ofnode subnode;
be789092 SG	249	int err;
1680d7b6	250
be789092	251	err = ofnode_read_resource(node, 0, &padctl->regs);
1680d7b6	252	if (err < 0) {
9b643e31	253	pr_err("registers not found");
1680d7b6 SW	254	return err;
	255	}
	256
3991f42e	257	ofnode_for_each_subnode(subnode, node) {
1680d7b6 SW	258	struct tegra_xusb_padctl_config *config = &padctl->config;
1680d7b6 SW	259
be789092 SG	260	debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
be789092 SG	261	err = tegra_xusb_padctl_config_parse_dt(padctl, config,
1680d7b6 SW	262	subnode);
1680d7b6 SW	263	if (err < 0) {
9b643e31	264	pr_err("failed to parse entry %s: %d",
1680d7b6 SW	265	config->name, err);
	266	continue;
	267	}
	268	}
be789092	269	debug("%s: done\n", __func__);
1680d7b6 SW	270
	271	return 0;
	272	}
	273
	274	struct tegra_xusb_padctl padctl;
	275
be789092 SG	276	int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
be789092 SG	277	const struct tegra_xusb_padctl_soc *socdata)
1680d7b6 SW	278	{
	279	unsigned int i;
	280	int err;
	281
be789092	282	debug("%s: count=%d\n", __func__, count);
1680d7b6	283	for (i = 0; i < count; i++) {
be789092 SG	284	debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
be789092 SG	285	if (!ofnode_is_available(nodes[i]))
1680d7b6 SW	286	continue;
	287
	288	padctl.socdata = socdata;
	289
be789092	290	err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
1680d7b6	291	if (err < 0) {
9b643e31	292	pr_err("failed to parse DT: %d", err);
1680d7b6 SW	293	continue;
	294	}
	295
	296	/* deassert XUSB padctl reset */
	297	reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
	298
	299	err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
	300	if (err < 0) {
9b643e31	301	pr_err("failed to apply pinmux: %d", err);
1680d7b6 SW	302	continue;
	303	}
	304
	305	/* only a single instance is supported */
	306	break;
	307	}
be789092	308	debug("%s: done\n", __func__);
1680d7b6 SW	309
	310	return 0;
	311	}