[people/ms/u-boot.git] / arch / arm / mach-uniphier / arm64 / arm-cci500.c

/*
 * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
 *
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>

#include "../init.h"

#define CCI500_BASE			0x5FD00000
#define CCI500_SLAVE_OFFSET		0x1000

#define CCI500_SNOOP_CTRL
#define   CCI500_SNOOP_CTRL_EN_DVM	BIT(1)
#define   CCI500_SNOOP_CTRL_EN_SNOOP	BIT(0)

void cci500_init(unsigned int nr_slaves)
{
	unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
	int i;

	for (i = 0; i < nr_slaves; i++) {
		void __iomem *base;
		u32 tmp;

		base = ioremap(slave_base, SZ_4K);

		tmp = readl(base);
		tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
		writel(tmp, base);

		iounmap(base);

		slave_base += CCI500_SLAVE_OFFSET;
	}
}
Commit	Line	Data
9d0c2ceb MY	1	/*
	2	* Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
	3	*
4e3d8406 MY	4	* Copyright (C) 2016 Socionext Inc.
4e3d8406 MY	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
9d0c2ceb MY	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
9d0c2ceb MY	10	#include <linux/bitops.h>
	11	#include <linux/io.h>
	12	#include <linux/sizes.h>
	13
1d21e1b9 MY	14	#include "../init.h"
1d21e1b9 MY	15
9d0c2ceb MY	16	#define CCI500_BASE 0x5FD00000
	17	#define CCI500_SLAVE_OFFSET 0x1000
	18
	19	#define CCI500_SNOOP_CTRL
	20	#define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
	21	#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
	22
	23	void cci500_init(unsigned int nr_slaves)
	24	{
	25	unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
	26	int i;
	27
	28	for (i = 0; i < nr_slaves; i++) {
	29	void __iomem *base;
	30	u32 tmp;
	31
4e3d8406	32	base = ioremap(slave_base, SZ_4K);
9d0c2ceb MY	33
	34	tmp = readl(base);
	35	tmp \|= CCI500_SNOOP_CTRL_EN_DVM \| CCI500_SNOOP_CTRL_EN_SNOOP;
	36	writel(tmp, base);
	37
4e3d8406	38	iounmap(base);
9d0c2ceb MY	39
	40	slave_base += CCI500_SLAVE_OFFSET;
	41	}
	42	}