projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9d0c2ceb MY |
1 | /* |
| 2 | * Copyright (C) 2016 Socionext Inc. | |
| f9d7e17e MY |
3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 9d0c2ceb MY |
5 | */ |
| 6 | ||
| 7 | #ifndef _DDRPHY_LD20_REGS_H | |
| 8 | #define _DDRPHY_LD20_REGS_H | |
| 9 | ||
| c89638a0 MY |
10 | #include <linux/bitops.h> |
| 11 | ||
| f9d7e17e | 12 | #define PHY_REG_SHIFT 2 |
| c89638a0 MY |
13 | #define PHY_SLV_DLY_WIDTH 6 |
| 14 | #define PHY_BITLVL_DLY_WIDTH 6 | |
| 15 | #define PHY_MAS_DLY_WIDTH 8 | |
| f9d7e17e MY |
16 | |
| 17 | #define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) | |
| 18 | #define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) | |
| 19 | #define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT)) | |
| 20 | #define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT)) | |
| 21 | #define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT)) | |
| 22 | #define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT)) | |
| 23 | #define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT)) | |
| 24 | #define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT)) | |
| c89638a0 MY |
25 | #define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) |
| 26 | #define PHY_DLL_RECALIB_INCR BIT(27) | |
| f9d7e17e | 27 | #define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT)) |
| c89638a0 MY |
28 | #define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) |
| 29 | #define PHY_DLL_ADRCTRL_INCR BIT(9) | |
| 30 | #define PHY_DLL_ADRCTRL_MDL_SHIFT 24 | |
| 31 | #define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \ | |
| 32 | PHY_DLL_ADRCTRL_MDL_SHIFT) | |
| f9d7e17e | 33 | #define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT)) |
| c89638a0 MY |
34 | #define PHY_LANE_SEL_LANE_SHIFT 0 |
| 35 | #define PHY_LANE_SEL_LANE_WIDTH 8 | |
| 36 | #define PHY_LANE_SEL_BIT_SHIFT 8 | |
| 37 | #define PHY_LANE_SEL_BIT_WIDTH 4 | |
| f9d7e17e MY |
38 | #define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT)) |
| 39 | #define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT)) | |
| 40 | #define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT)) | |
| 41 | #define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT)) | |
| 42 | #define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT)) | |
| 43 | #define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT)) | |
| 44 | #define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT)) | |
| 45 | #define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT)) | |
| 46 | #define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT)) | |
| 47 | #define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT)) | |
| 48 | #define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT)) | |
| 49 | #define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT)) | |
| 50 | #define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT)) | |
| 51 | #define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT)) | |
| 52 | #define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT)) | |
| c89638a0 MY |
53 | #define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \ |
| 54 | GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) | |
| 55 | #define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \ | |
| 56 | BIT(PHY_BITLVL_DLY_WIDTH) | |
| 57 | #define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \ | |
| 58 | BIT(PHY_BITLVL_DLY_WIDTH + 1) | |
| f9d7e17e MY |
59 | #define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT)) |
| 60 | #define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT)) | |
| c89638a0 MY |
61 | #define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \ |
| 62 | GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) | |
| 63 | #define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \ | |
| 64 | BIT(PHY_BITLVL_DLY_WIDTH) | |
| 65 | #define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \ | |
| 66 | BIT(PHY_BITLVL_DLY_WIDTH + 1) | |
| f9d7e17e | 67 | #define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT)) |
| c89638a0 MY |
68 | #define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0) |
| 69 | #define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1) | |
| f9d7e17e MY |
70 | #define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT)) |
| 71 | #define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT)) | |
| 72 | #define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT)) | |
| 73 | #define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT)) | |
| 74 | #define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT)) | |
| 75 | #define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT)) | |
| 76 | #define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT)) | |
| 77 | ||
| 9d0c2ceb | 78 | #endif /* _DDRPHY_LD20_REGS_H */ |