[people/ms/u-boot.git] / arch / arm / mach-uniphier / memconf / memconf.c

/*
 * Copyright (C) 2011-2015 Panasonic Corporation
 * Copyright (C) 2016      Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sizes.h>

#include "../init.h"
#include "../sg-regs.h"

int memconf_init(const struct uniphier_board_data *bd)
{
	u32 tmp;
	unsigned long size_per_word;

	tmp = readl(SG_MEMCONF);

	tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);

	switch (bd->dram_ch[0].width) {
	case 16:
		tmp |= SG_MEMCONF_CH0_NUM_1;
		size_per_word = bd->dram_ch[0].size;
		break;
	case 32:
		tmp |= SG_MEMCONF_CH0_NUM_2;
		size_per_word = bd->dram_ch[0].size >> 1;
		break;
	default:
		pr_err("error: unsupported DRAM Ch0 width\n");
		return -EINVAL;
	}

	/* Set DDR size */
	switch (size_per_word) {
	case SZ_64M:
		tmp |= SG_MEMCONF_CH0_SZ_64M;
		break;
	case SZ_128M:
		tmp |= SG_MEMCONF_CH0_SZ_128M;
		break;
	case SZ_256M:
		tmp |= SG_MEMCONF_CH0_SZ_256M;
		break;
	case SZ_512M:
		tmp |= SG_MEMCONF_CH0_SZ_512M;
		break;
	case SZ_1G:
		tmp |= SG_MEMCONF_CH0_SZ_1G;
		break;
	default:
		pr_err("error: unsupported DRAM Ch0 size\n");
		return -EINVAL;
	}

	tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);

	switch (bd->dram_ch[1].width) {
	case 16:
		tmp |= SG_MEMCONF_CH1_NUM_1;
		size_per_word = bd->dram_ch[1].size;
		break;
	case 32:
		tmp |= SG_MEMCONF_CH1_NUM_2;
		size_per_word = bd->dram_ch[1].size >> 1;
		break;
	default:
		pr_err("error: unsupported DRAM Ch1 width\n");
		return -EINVAL;
	}

	switch (size_per_word) {
	case SZ_64M:
		tmp |= SG_MEMCONF_CH1_SZ_64M;
		break;
	case SZ_128M:
		tmp |= SG_MEMCONF_CH1_SZ_128M;
		break;
	case SZ_256M:
		tmp |= SG_MEMCONF_CH1_SZ_256M;
		break;
	case SZ_512M:
		tmp |= SG_MEMCONF_CH1_SZ_512M;
		break;
	case SZ_1G:
		tmp |= SG_MEMCONF_CH1_SZ_1G;
		break;
	default:
		pr_err("error: unsupported DRAM Ch1 size\n");
		return -EINVAL;
	}

	if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
		tmp |= SG_MEMCONF_SPARSEMEM;
	else
		tmp &= ~SG_MEMCONF_SPARSEMEM;

	writel(tmp, SG_MEMCONF);

	return 0;
}
Commit	Line	Data
323d1f9d	1	/*
82ff6c39 MY	2	* Copyright (C) 2011-2015 Panasonic Corporation
	3	* Copyright (C) 2016 Socionext Inc.
	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
323d1f9d MY	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/sizes.h>
107b3fb4 MY	13
	14	#include "../init.h"
	15	#include "../sg-regs.h"
323d1f9d MY	16
	17	int memconf_init(const struct uniphier_board_data *bd)
	18	{
82ff6c39	19	u32 tmp;
323d1f9d MY	20	unsigned long size_per_word;
	21
	22	tmp = readl(SG_MEMCONF);
	23
	24	tmp &= ~(SG_MEMCONF_CH0_SZ_MASK \| SG_MEMCONF_CH0_NUM_MASK);
	25
46abfcc9	26	switch (bd->dram_ch[0].width) {
323d1f9d MY	27	case 16:
323d1f9d MY	28	tmp \|= SG_MEMCONF_CH0_NUM_1;
46abfcc9	29	size_per_word = bd->dram_ch[0].size;
323d1f9d MY	30	break;
	31	case 32:
	32	tmp \|= SG_MEMCONF_CH0_NUM_2;
46abfcc9	33	size_per_word = bd->dram_ch[0].size >> 1;
323d1f9d MY	34	break;
	35	default:
	36	pr_err("error: unsupported DRAM Ch0 width\n");
	37	return -EINVAL;
	38	}
	39
	40	/* Set DDR size */
	41	switch (size_per_word) {
	42	case SZ_64M:
	43	tmp \|= SG_MEMCONF_CH0_SZ_64M;
	44	break;
	45	case SZ_128M:
	46	tmp \|= SG_MEMCONF_CH0_SZ_128M;
	47	break;
	48	case SZ_256M:
	49	tmp \|= SG_MEMCONF_CH0_SZ_256M;
	50	break;
	51	case SZ_512M:
	52	tmp \|= SG_MEMCONF_CH0_SZ_512M;
	53	break;
	54	case SZ_1G:
	55	tmp \|= SG_MEMCONF_CH0_SZ_1G;
	56	break;
	57	default:
	58	pr_err("error: unsupported DRAM Ch0 size\n");
	59	return -EINVAL;
	60	}
	61
	62	tmp &= ~(SG_MEMCONF_CH1_SZ_MASK \| SG_MEMCONF_CH1_NUM_MASK);
	63
46abfcc9	64	switch (bd->dram_ch[1].width) {
323d1f9d MY	65	case 16:
323d1f9d MY	66	tmp \|= SG_MEMCONF_CH1_NUM_1;
46abfcc9	67	size_per_word = bd->dram_ch[1].size;
323d1f9d MY	68	break;
	69	case 32:
	70	tmp \|= SG_MEMCONF_CH1_NUM_2;
46abfcc9	71	size_per_word = bd->dram_ch[1].size >> 1;
323d1f9d MY	72	break;
	73	default:
	74	pr_err("error: unsupported DRAM Ch1 width\n");
	75	return -EINVAL;
	76	}
	77
	78	switch (size_per_word) {
	79	case SZ_64M:
	80	tmp \|= SG_MEMCONF_CH1_SZ_64M;
	81	break;
	82	case SZ_128M:
	83	tmp \|= SG_MEMCONF_CH1_SZ_128M;
	84	break;
	85	case SZ_256M:
	86	tmp \|= SG_MEMCONF_CH1_SZ_256M;
	87	break;
	88	case SZ_512M:
	89	tmp \|= SG_MEMCONF_CH1_SZ_512M;
	90	break;
	91	case SZ_1G:
	92	tmp \|= SG_MEMCONF_CH1_SZ_1G;
	93	break;
	94	default:
	95	pr_err("error: unsupported DRAM Ch1 size\n");
	96	return -EINVAL;
	97	}
	98
46abfcc9	99	if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
323d1f9d MY	100	tmp \|= SG_MEMCONF_SPARSEMEM;
	101	else
	102	tmp &= ~SG_MEMCONF_SPARSEMEM;
	103
	104	writel(tmp, SG_MEMCONF);
	105
	106	return 0;
	107	}