[people/ms/u-boot.git] / arch / avr32 / cpu / start.S

/*
 * Copyright (C) 2005-2008 Atmel Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <asm-offsets.h>
#include <config.h>
#include <asm/ptrace.h>
#include <asm/sysreg.h>

#define SYSREG_MMUCR_I_OFFSET	2
#define SYSREG_MMUCR_S_OFFSET	4

#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
/* due to errata (unreliable branch folding) clear FE bit explicitly */
#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE)	\
		    | SYSREG_BIT(RE)   |  SYSREG_BIT(IBE)		\
		    | SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))

	/*
	 * To save some space, we use the same entry point for
	 * exceptions and reset. This avoids lots of alignment padding
	 * since the reset vector is always suitably aligned.
	 */
	.section .exception.text, "ax", @progbits
	.global	_start
	.global	_evba
	.type	_start, @function
	.type	_evba, @function
_start:
	.size	_start, 0
_evba:
	.org	0x00
	rjmp	unknown_exception	/* Unrecoverable exception */
	.org	0x04
	rjmp	unknown_exception	/* TLB multiple hit */
	.org	0x08
	rjmp	unknown_exception	/* Bus error data fetch */
	.org	0x0c
	rjmp	unknown_exception	/* Bus error instruction fetch */
	.org	0x10
	rjmp	unknown_exception	/* NMI */
	.org	0x14
	rjmp	unknown_exception	/* Instruction address */
	.org	0x18
	rjmp	unknown_exception	/* ITLB protection */
	.org	0x1c
	rjmp	unknown_exception	/* Breakpoint */
	.org	0x20
	rjmp	unknown_exception	/* Illegal opcode */
	.org	0x24
	rjmp	unknown_exception	/* Unimplemented instruction */
	.org	0x28
	rjmp	unknown_exception	/* Privilege violation */
	.org	0x2c
	rjmp	unknown_exception	/* Floating-point */
	.org	0x30
	rjmp	unknown_exception	/* Coprocessor absent */
	.org	0x34
	rjmp	unknown_exception	/* Data Address (read) */
	.org	0x38
	rjmp	unknown_exception	/* Data Address (write) */
	.org	0x3c
	rjmp	unknown_exception	/* DTLB Protection (read) */
	.org	0x40
	rjmp	unknown_exception	/* DTLB Protection (write) */
	.org	0x44
	rjmp	unknown_exception	/* DTLB Modified */

	.org	0x50			/* ITLB Miss */
	pushm   r8-r12,lr
	rjmp	1f
	.org	0x60			/* DTLB Miss (read) */
	pushm   r8-r12,lr
	rjmp	1f
	.org	0x70			/* DTLB Miss (write) */
	pushm   r8-r12,lr
1:	mov	r12, sp
	rcall	mmu_handle_tlb_miss
	popm	r8-r12,lr
	brne	unknown_exception
	rete

	.size	_evba, . - _evba

	.align	2
	.type	unknown_exception, @function
unknown_exception:
	/* Figure out whether we're handling an exception (Exception
	 * mode) or just booting (Supervisor mode). */
	csrfcz	SYSREG_M1_OFFSET
	brcc	at32ap_cpu_bootstrap

	/* This is an exception. Complain. */
	pushm	r0-r12
	sub	r8, sp, REG_R12 - REG_R0 - 4
	mov	r9, lr
	mfsr	r10, SYSREG_RAR_EX
	mfsr	r11, SYSREG_RSR_EX
	pushm	r8-r11
	mfsr	r12, SYSREG_ECR
	mov	r11, sp
	rcall	do_unknown_exception
1:	rjmp	1b

	/* The COUNT/COMPARE timer interrupt handler */
	.global	timer_interrupt_handler
	.type	timer_interrupt_handler,@function
	.align	2
timer_interrupt_handler:
	/*
	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
	 *
	 * We're running at interrupt level 3, so we don't need to save
	 * r8-r12 or lr to the stack.
	 */
	lda.w	r8, timer_overflow
	ld.w	r9, r8[0]
	mov	r10, -1
	mtsr	SYSREG_COMPARE, r10
	sub	r9, -1
	st.w	r8[0], r9
	rete

	/*
	 * CPU bootstrap after reset is handled here. SoC code may
	 * override this in case they need to initialize oscillators,
	 * etc.
	 */
	.section .text.at32ap_cpu_bootstrap, "ax", @progbits
	.global	at32ap_cpu_bootstrap
	.weak	at32ap_cpu_bootstrap
	.type	at32ap_cpu_bootstrap, @function
	.align	2
at32ap_cpu_bootstrap:
	/* Reset the Status Register */
	mov	r0, lo(SR_INIT)
	orh	r0, hi(SR_INIT)
	mtsr	SYSREG_SR, r0

	/* Reset CPUCR and invalidate the BTB */
	mov	r2, CPUCR_INIT
	mtsr	SYSREG_CPUCR, r2

	/* Flush the caches */
	mov	r1, 0
	cache	r1[4], 8
	cache	r1[0], 0
	sync	0

	/* Reset the MMU to default settings */
	mov	r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
	mtsr	SYSREG_MMUCR, r0

	/* Internal RAM should not need any initialization.  We might
	   have to initialize external RAM here if the part doesn't
	   have internal RAM (or we may use the data cache) */

	/* Jump to cacheable segment */
	lddpc	pc, 1f

	.align	2
1:	.long	at32ap_low_level_init
	.size	_start, . - _start

	/* Common CPU bootstrap code after oscillator/cache/etc. init */
	.section .text.avr32ap_low_level_init, "ax", @progbits
	.global	at32ap_low_level_init
	.type	at32ap_low_level_init, @function
	.align	2
at32ap_low_level_init:
	lddpc	sp, sp_init

	/* Initialize the GOT pointer */
	lddpc	r6, got_init
3:	rsub	r6, pc

	/* Let's go */
	rjmp	board_init_f

	.align	2
	.type	sp_init,@object
sp_init:
	.long	CONFIG_SYS_INIT_SP_ADDR
got_init:
	.long	3b - _GLOBAL_OFFSET_TABLE_

	/*
	 * void	relocate_code(new_sp, new_gd, monitor_addr)
	 *
	 * Relocate the u-boot image into RAM and continue from there.
	 * Does not return.
	 */
	.section .text.relocate_code,"ax",@progbits
	.global	relocate_code
	.type	relocate_code,@function
relocate_code:
	mov	sp, r12		/* use new stack */
	mov	r12, r11	/* save new_gd */
	mov	r11, r10	/* save destination address */

	/* copy .text section and flush the cache along the way */
	lda.w	r8, _text
	lda.w	r9, _etext
	sub	lr, r10, r8	/* relocation offset */

1:	ldm	r8++, r0-r3
	stm	r10, r0-r3
	sub	r10, -16
	ldm	r8++, r0-r3
	stm	r10, r0-r3
	sub	r10, -16
	cp.w	r8, r9
	cache	r10[-4], 0x0d	/* dcache clean/invalidate */
	cache	r10[-4], 0x01	/* icache invalidate */
	brlt	1b

	/* flush write buffer */
	sync	0

	/* copy data sections */
	lda.w	r9, _edata
1:	ld.d	r0, r8++
	st.d	r10++, r0
	cp.w	r8, r9
	brlt	1b

	/* zero out .bss */
	mov	r0, 0
	mov	r1, 0
	lda.w	r9, __bss_end
	sub	r9, r8
1:	st.d	r10++, r0
	sub	r9, 8
	brgt	1b

	/* jump to RAM */
	sub	r0, pc, . - in_ram
	add	pc, r0, lr

	.align	2
in_ram:
	/* find the new GOT and relocate it */
	lddpc	r6, got_init_reloc
3:	rsub	r6, pc
	mov	r8, r6
	lda.w	r9, _egot
	lda.w	r10, _got
	sub	r9, r10
1:	ld.w	r0, r8[0]
	add	r0, lr
	st.w	r8++, r0
	sub	r9, 4
	brgt	1b

	/* Move the exception handlers */
	mfsr	r2, SYSREG_EVBA
	add	r2, lr
	mtsr	SYSREG_EVBA, r2

	/* Do the rest of the initialization sequence */
	call	board_init_r

	.align	2
got_init_reloc:
	.long	3b - _GLOBAL_OFFSET_TABLE_

	.size	relocate_code, . - relocate_code
Commit	Line	Data
72a087e0	1	/*
caf83ea8	2	* Copyright (C) 2005-2008 Atmel Corporation
72a087e0	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
72a087e0	5	*/
25ddd1fb	6	#include <asm-offsets.h>
72a087e0	7	#include <config.h>
caf83ea8	8	#include <asm/ptrace.h>
72a087e0 WD	9	#include <asm/sysreg.h>
72a087e0 WD	10
72a087e0 WD	11	#define SYSREG_MMUCR_I_OFFSET 2
	12	#define SYSREG_MMUCR_S_OFFSET 4
	13
	14	#define SR_INIT (SYSREG_BIT(GM) \| SYSREG_BIT(EM) \| SYSREG_BIT(M0))
eb70d05d AB	15	/* due to errata (unreliable branch folding) clear FE bit explicitly */
	16	#define CPUCR_INIT ((SYSREG_BIT(BI) \| SYSREG_BIT(BE) \
	17	\| SYSREG_BIT(RE) \| SYSREG_BIT(IBE) \
	18	\| SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))
72a087e0	19
caf83ea8 HS	20	/*
	21	* To save some space, we use the same entry point for
	22	* exceptions and reset. This avoids lots of alignment padding
	23	* since the reset vector is always suitably aligned.
	24	*/
	25	.section .exception.text, "ax", @progbits
72a087e0	26	.global _start
caf83ea8 HS	27	.global _evba
	28	.type _start, @function
	29	.type _evba, @function
72a087e0	30	_start:
caf83ea8 HS	31	.size _start, 0
	32	_evba:
	33	.org 0x00
	34	rjmp unknown_exception /* Unrecoverable exception */
	35	.org 0x04
	36	rjmp unknown_exception /* TLB multiple hit */
	37	.org 0x08
	38	rjmp unknown_exception /* Bus error data fetch */
	39	.org 0x0c
	40	rjmp unknown_exception /* Bus error instruction fetch */
	41	.org 0x10
	42	rjmp unknown_exception /* NMI */
	43	.org 0x14
	44	rjmp unknown_exception /* Instruction address */
	45	.org 0x18
	46	rjmp unknown_exception /* ITLB protection */
	47	.org 0x1c
	48	rjmp unknown_exception /* Breakpoint */
	49	.org 0x20
	50	rjmp unknown_exception /* Illegal opcode */
	51	.org 0x24
	52	rjmp unknown_exception /* Unimplemented instruction */
	53	.org 0x28
	54	rjmp unknown_exception /* Privilege violation */
	55	.org 0x2c
	56	rjmp unknown_exception /* Floating-point */
	57	.org 0x30
	58	rjmp unknown_exception /* Coprocessor absent */
	59	.org 0x34
	60	rjmp unknown_exception /* Data Address (read) */
	61	.org 0x38
	62	rjmp unknown_exception /* Data Address (write) */
	63	.org 0x3c
	64	rjmp unknown_exception /* DTLB Protection (read) */
	65	.org 0x40
	66	rjmp unknown_exception /* DTLB Protection (write) */
	67	.org 0x44
	68	rjmp unknown_exception /* DTLB Modified */
	69
1f36f73f HS	70	.org 0x50 /* ITLB Miss */
	71	pushm r8-r12,lr
	72	rjmp 1f
	73	.org 0x60 /* DTLB Miss (read) */
	74	pushm r8-r12,lr
	75	rjmp 1f
	76	.org 0x70 /* DTLB Miss (write) */
	77	pushm r8-r12,lr
	78	1: mov r12, sp
	79	rcall mmu_handle_tlb_miss
	80	popm r8-r12,lr
	81	brne unknown_exception
	82	rete
caf83ea8 HS	83
	84	.size _evba, . - _evba
	85
	86	.align 2
	87	.type unknown_exception, @function
	88	unknown_exception:
	89	/* Figure out whether we're handling an exception (Exception
	90	* mode) or just booting (Supervisor mode). */
	91	csrfcz SYSREG_M1_OFFSET
	92	brcc at32ap_cpu_bootstrap
	93
	94	/* This is an exception. Complain. */
	95	pushm r0-r12
	96	sub r8, sp, REG_R12 - REG_R0 - 4
	97	mov r9, lr
	98	mfsr r10, SYSREG_RAR_EX
	99	mfsr r11, SYSREG_RSR_EX
	100	pushm r8-r11
	101	mfsr r12, SYSREG_ECR
	102	mov r11, sp
	103	rcall do_unknown_exception
	104	1: rjmp 1b
	105
	106	/* The COUNT/COMPARE timer interrupt handler */
	107	.global timer_interrupt_handler
	108	.type timer_interrupt_handler,@function
	109	.align 2
	110	timer_interrupt_handler:
	111	/*
	112	* Increment timer_overflow and re-write COMPARE with 0xffffffff.
	113	*
	114	* We're running at interrupt level 3, so we don't need to save
	115	* r8-r12 or lr to the stack.
	116	*/
	117	lda.w r8, timer_overflow
	118	ld.w r9, r8[0]
	119	mov r10, -1
	120	mtsr SYSREG_COMPARE, r10
	121	sub r9, -1
	122	st.w r8[0], r9
	123	rete
72a087e0	124
caf83ea8 HS	125	/*
	126	* CPU bootstrap after reset is handled here. SoC code may
	127	* override this in case they need to initialize oscillators,
	128	* etc.
	129	*/
	130	.section .text.at32ap_cpu_bootstrap, "ax", @progbits
	131	.global at32ap_cpu_bootstrap
	132	.weak at32ap_cpu_bootstrap
	133	.type at32ap_cpu_bootstrap, @function
	134	.align 2
	135	at32ap_cpu_bootstrap:
72a087e0 WD	136	/* Reset the Status Register */
	137	mov r0, lo(SR_INIT)
	138	orh r0, hi(SR_INIT)
	139	mtsr SYSREG_SR, r0
	140
	141	/* Reset CPUCR and invalidate the BTB */
	142	mov r2, CPUCR_INIT
	143	mtsr SYSREG_CPUCR, r2
	144
	145	/* Flush the caches */
	146	mov r1, 0
	147	cache r1[4], 8
	148	cache r1[0], 0
	149	sync 0
	150
	151	/* Reset the MMU to default settings */
	152	mov r0, SYSREG_BIT(MMUCR_S) \| SYSREG_BIT(MMUCR_I)
	153	mtsr SYSREG_MMUCR, r0
	154
	155	/* Internal RAM should not need any initialization. We might
	156	have to initialize external RAM here if the part doesn't
	157	have internal RAM (or we may use the data cache) */
	158
	159	/* Jump to cacheable segment */
	160	lddpc pc, 1f
	161
	162	.align 2
caf83ea8 HS	163	1: .long at32ap_low_level_init
caf83ea8 HS	164	.size _start, . - _start
72a087e0	165
caf83ea8 HS	166	/* Common CPU bootstrap code after oscillator/cache/etc. init */
	167	.section .text.avr32ap_low_level_init, "ax", @progbits
	168	.global at32ap_low_level_init
	169	.type at32ap_low_level_init, @function
	170	.align 2
	171	at32ap_low_level_init:
	172	lddpc sp, sp_init
72a087e0	173
72a087e0 WD	174	/* Initialize the GOT pointer */
	175	lddpc r6, got_init
	176	3: rsub r6, pc
1f4f2121 HS	177
	178	/* Let's go */
	179	rjmp board_init_f
72a087e0 WD	180
	181	.align 2
	182	.type sp_init,@object
	183	sp_init:
6d0f6bcf	184	.long CONFIG_SYS_INIT_SP_ADDR
72a087e0 WD	185	got_init:
72a087e0 WD	186	.long 3b - _GLOBAL_OFFSET_TABLE_
1f4f2121 HS	187
	188	/*
	189	* void relocate_code(new_sp, new_gd, monitor_addr)
	190	*
	191	* Relocate the u-boot image into RAM and continue from there.
	192	* Does not return.
	193	*/
caf83ea8	194	.section .text.relocate_code,"ax",@progbits
1f4f2121 HS	195	.global relocate_code
	196	.type relocate_code,@function
	197	relocate_code:
	198	mov sp, r12 /* use new stack */
	199	mov r12, r11 /* save new_gd */
	200	mov r11, r10 /* save destination address */
	201
	202	/* copy .text section and flush the cache along the way */
	203	lda.w r8, _text
	204	lda.w r9, _etext
	205	sub lr, r10, r8 /* relocation offset */
	206
	207	1: ldm r8++, r0-r3
	208	stm r10, r0-r3
	209	sub r10, -16
	210	ldm r8++, r0-r3
	211	stm r10, r0-r3
	212	sub r10, -16
	213	cp.w r8, r9
	214	cache r10[-4], 0x0d /* dcache clean/invalidate */
	215	cache r10[-4], 0x01 /* icache invalidate */
	216	brlt 1b
	217
	218	/* flush write buffer */
	219	sync 0
	220
	221	/* copy data sections */
	222	lda.w r9, _edata
	223	1: ld.d r0, r8++
	224	st.d r10++, r0
	225	cp.w r8, r9
	226	brlt 1b
	227
	228	/* zero out .bss */
	229	mov r0, 0
	230	mov r1, 0
3929fb0a	231	lda.w r9, __bss_end
1f4f2121 HS	232	sub r9, r8
	233	1: st.d r10++, r0
	234	sub r9, 8
	235	brgt 1b
	236
	237	/* jump to RAM */
	238	sub r0, pc, . - in_ram
	239	add pc, r0, lr
	240
	241	.align 2
	242	in_ram:
	243	/* find the new GOT and relocate it */
	244	lddpc r6, got_init_reloc
	245	3: rsub r6, pc
	246	mov r8, r6
	247	lda.w r9, _egot
	248	lda.w r10, _got
	249	sub r9, r10
	250	1: ld.w r0, r8[0]
	251	add r0, lr
	252	st.w r8++, r0
	253	sub r9, 4
	254	brgt 1b
	255
	256	/* Move the exception handlers */
	257	mfsr r2, SYSREG_EVBA
	258	add r2, lr
	259	mtsr SYSREG_EVBA, r2
	260
	261	/* Do the rest of the initialization sequence */
	262	call board_init_r
	263
	264	.align 2
	265	got_init_reloc:
	266	.long 3b - _GLOBAL_OFFSET_TABLE_
caf83ea8 HS	267
caf83ea8 HS	268	.size relocate_code, . - relocate_code