]>
Commit | Line | Data |
---|---|---|
7b64fef3 WD |
1 | /* |
2 | * Copyright (C) 2006 Atmel Corporation | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | #ifndef __ASM_AVR32_CACHEFLUSH_H | |
23 | #define __ASM_AVR32_CACHEFLUSH_H | |
24 | ||
25 | /* | |
26 | * Invalidate any cacheline containing virtual address vaddr without | |
27 | * writing anything back to memory. | |
28 | * | |
29 | * Note that this function may corrupt unrelated data structures when | |
30 | * applied on buffers that are not cacheline aligned in both ends. | |
31 | */ | |
32 | static inline void dcache_invalidate_line(volatile void *vaddr) | |
33 | { | |
34 | asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory"); | |
35 | } | |
36 | ||
37 | /* | |
38 | * Make sure any cacheline containing virtual address vaddr is written | |
39 | * to memory. | |
40 | */ | |
41 | static inline void dcache_clean_line(volatile void *vaddr) | |
42 | { | |
43 | asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory"); | |
44 | } | |
45 | ||
46 | /* | |
47 | * Make sure any cacheline containing virtual address vaddr is written | |
48 | * to memory and then invalidate it. | |
49 | */ | |
50 | static inline void dcache_flush_line(volatile void *vaddr) | |
51 | { | |
52 | asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory"); | |
53 | } | |
54 | ||
55 | /* | |
56 | * Invalidate any instruction cacheline containing virtual address | |
57 | * vaddr. | |
58 | */ | |
59 | static inline void icache_invalidate_line(volatile void *vaddr) | |
60 | { | |
61 | asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory"); | |
62 | } | |
63 | ||
64 | /* | |
65 | * Applies the above functions on all lines that are touched by the | |
66 | * specified virtual address range. | |
67 | */ | |
68 | void dcache_invalidate_range(volatile void *start, size_t len); | |
69 | void dcache_clean_range(volatile void *start, size_t len); | |
70 | void dcache_flush_range(volatile void *start, size_t len); | |
71 | void icache_invalidate_range(volatile void *start, size_t len); | |
72 | ||
73 | static inline void dcache_flush_unlocked(void) | |
74 | { | |
75 | asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory"); | |
76 | } | |
77 | ||
78 | /* | |
79 | * Make sure any pending writes are completed before continuing. | |
80 | */ | |
81 | #define sync_write_buffer() asm volatile("sync 0" : : : "memory") | |
82 | ||
83 | #endif /* __ASM_AVR32_CACHEFLUSH_H */ |