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7b64fef3 WD |
1 | /* |
2 | * Copyright (C) 2006 Atmel Corporation | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
7b64fef3 WD |
5 | */ |
6 | #ifndef __ASM_AVR32_PTRACE_H | |
7 | #define __ASM_AVR32_PTRACE_H | |
8 | ||
9 | /* | |
10 | * Status Register bits | |
11 | */ | |
12 | #define SR_H 0x40000000 | |
13 | #define SR_R 0x20000000 | |
14 | #define SR_J 0x10000000 | |
15 | #define SR_DM 0x08000000 | |
16 | #define SR_D 0x04000000 | |
17 | #define MODE_NMI 0x01c00000 | |
18 | #define MODE_EXCEPTION 0x01800000 | |
19 | #define MODE_INT3 0x01400000 | |
20 | #define MODE_INT2 0x01000000 | |
21 | #define MODE_INT1 0x00c00000 | |
22 | #define MODE_INT0 0x00800000 | |
23 | #define MODE_SUPERVISOR 0x00400000 | |
24 | #define MODE_USER 0x00000000 | |
25 | #define MODE_MASK 0x01c00000 | |
26 | #define SR_EM 0x00200000 | |
27 | #define SR_I3M 0x00100000 | |
28 | #define SR_I2M 0x00080000 | |
29 | #define SR_I1M 0x00040000 | |
30 | #define SR_I0M 0x00020000 | |
31 | #define SR_GM 0x00010000 | |
32 | ||
33 | #define MODE_SHIFT 22 | |
34 | #define SR_EM_BIT 21 | |
35 | #define SR_I3M_BIT 20 | |
36 | #define SR_I2M_BIT 19 | |
37 | #define SR_I1M_BIT 18 | |
38 | #define SR_I0M_BIT 17 | |
39 | #define SR_GM_BIT 16 | |
40 | ||
41 | /* The user-visible part */ | |
42 | #define SR_Q 0x00000010 | |
43 | #define SR_V 0x00000008 | |
44 | #define SR_N 0x00000004 | |
45 | #define SR_Z 0x00000002 | |
46 | #define SR_C 0x00000001 | |
47 | ||
48 | /* | |
49 | * The order is defined by the stdsp instruction. r0 is stored first, so it | |
50 | * gets the highest address. | |
51 | * | |
52 | * Registers 0-12 are general-purpose registers (r12 is normally used for | |
53 | * the function return value). | |
54 | * Register 13 is the stack pointer | |
55 | * Register 14 is the link register | |
56 | * Register 15 is the program counter | |
57 | */ | |
58 | #define FRAME_SIZE_FULL 72 | |
59 | #define REG_R12_ORIG 68 | |
60 | #define REG_R0 64 | |
61 | #define REG_R1 60 | |
62 | #define REG_R2 56 | |
63 | #define REG_R3 52 | |
64 | #define REG_R4 48 | |
65 | #define REG_R5 44 | |
66 | #define REG_R6 40 | |
67 | #define REG_R7 36 | |
68 | #define REG_R8 32 | |
69 | #define REG_R9 28 | |
70 | #define REG_R10 34 | |
71 | #define REG_R11 20 | |
72 | #define REG_R12 16 | |
73 | #define REG_SP 12 | |
74 | #define REG_LR 8 | |
75 | ||
76 | #define FRAME_SIZE_MIN 8 | |
77 | #define REG_PC 4 | |
78 | #define REG_SR 0 | |
79 | ||
80 | #ifndef __ASSEMBLY__ | |
81 | struct pt_regs { | |
82 | /* These are always saved */ | |
83 | unsigned long sr; | |
84 | unsigned long pc; | |
85 | ||
86 | /* These are sometimes saved */ | |
87 | unsigned long lr; | |
88 | unsigned long sp; | |
89 | unsigned long r12; | |
90 | unsigned long r11; | |
91 | unsigned long r10; | |
92 | unsigned long r9; | |
93 | unsigned long r8; | |
94 | unsigned long r7; | |
95 | unsigned long r6; | |
96 | unsigned long r5; | |
97 | unsigned long r4; | |
98 | unsigned long r3; | |
99 | unsigned long r2; | |
100 | unsigned long r1; | |
101 | unsigned long r0; | |
102 | ||
103 | /* Only saved on system call */ | |
104 | unsigned long r12_orig; | |
105 | }; | |
106 | ||
107 | #ifdef __KERNEL__ | |
108 | # define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER) | |
109 | # define instruction_pointer(regs) ((regs)->pc) | |
110 | extern void show_regs (struct pt_regs *); | |
111 | ||
112 | static __inline__ int valid_user_regs(struct pt_regs *regs) | |
113 | { | |
114 | /* | |
115 | * Some of the Java bits might be acceptable if/when we | |
116 | * implement some support for that stuff... | |
117 | */ | |
118 | if ((regs->sr & 0xffff0000) == 0) | |
119 | return 1; | |
120 | ||
121 | /* | |
122 | * Force status register flags to be sane and report this | |
123 | * illegal behaviour... | |
124 | */ | |
125 | regs->sr &= 0x0000ffff; | |
126 | return 0; | |
127 | } | |
128 | #endif | |
129 | ||
130 | #endif /* ! __ASSEMBLY__ */ | |
131 | ||
132 | #endif /* __ASM_AVR32_PTRACE_H */ |