[people/ms/u-boot.git] / arch / blackfin / cpu / reset.c

/*
 * reset.c - logic for resetting the cpu
 *
 * Copyright (c) 2005-2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <common.h>
#include <command.h>
#include <asm/blackfin.h>
#include <asm/mach-common/bits/bootrom.h>
#include "cpu.h"

/* A system soft reset makes external memory unusable so force
 * this function into L1.  We use the compiler ssync here rather
 * than SSYNC() because it's safe (no interrupts and such) and
 * we save some L1.  We do not need to force sanity in the SYSCR
 * register as the BMODE selection bit is cleared by the soft
 * reset while the Core B bit (on dual core parts) is cleared by
 * the core reset.
 */
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
#ifdef SWRST
	/* Wait for completion of "system" events such as cache line
	 * line fills so that we avoid infinite stalls later on as
	 * much as possible.  This code is in L1, so it won't trigger
	 * any such event after this point in time.
	 */
	__builtin_bfin_ssync();

	/* Initiate System software reset. */
	bfin_write_SWRST(0x7);

	/* Due to the way reset is handled in the hardware, we need
	 * to delay for 10 SCLKS.  The only reliable way to do this is
	 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
	 * we'll assume worse case which is a 1:15 ratio.
	 */
	asm(
		"LSETUP (1f, 1f) LC0 = %0\n"
		"1: nop;"
		:
		: "a" (15 * 10)
		: "LC0", "LB0", "LT0"
	);

	/* Clear System software reset */
	bfin_write_SWRST(0);

	/* The BF526 ROM will crash during reset */
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
	/* Seems to be fixed with newer parts though ... */
	if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
		bfin_read_SWRST();
#endif

	/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
	 * though as the System state is all reset now.
	 */
	asm(
		"LSETUP (1f, 1f) LC1 = %0\n"
		"1: nop;"
		:
		: "a" (15 * 1)
		: "LC1", "LB1", "LT1"
	);
#endif

	while (1)
#if defined(__ADSPBF60x__)
		bfin_write_RCU0_CTL(0x1);
#else
		/* Issue core reset */
		asm("raise 1");
#endif
}

/* We need to trampoline ourselves up into L1 since our linker
 * does not have relaxtion support and will only generate a
 * PC relative call with a 25 bit immediate.  This is not enough
 * to get us from the top of SDRAM into L1.
 */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	if (board_reset)
		board_reset();
	if (ANOMALY_05000353 || ANOMALY_05000386)
		while (1)
			asm("jump (%0);" : : "a" (bfin_reset));
	else
		bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
	return 0;
}
Commit	Line	Data
9171fc81 MF	1	/*
	2	* reset.c - logic for resetting the cpu
	3	*
	4	* Copyright (c) 2005-2008 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2 or later.
	7	*/
	8
	9	#include <common.h>
	10	#include <command.h>
	11	#include <asm/blackfin.h>
9aeab10b	12	#include <asm/mach-common/bits/bootrom.h>
9171fc81 MF	13	#include "cpu.h"
	14
	15	/* A system soft reset makes external memory unusable so force
	16	* this function into L1. We use the compiler ssync here rather
	17	* than SSYNC() because it's safe (no interrupts and such) and
	18	* we save some L1. We do not need to force sanity in the SYSCR
	19	* register as the BMODE selection bit is cleared by the soft
	20	* reset while the Core B bit (on dual core parts) is cleared by
	21	* the core reset.
	22	*/
	23	__attribute__ ((__l1_text__, __noreturn__))
2decc2a8	24	static void bfin_reset(void)
9171fc81	25	{
a2979dcd	26	#ifdef SWRST
9171fc81 MF	27	/* Wait for completion of "system" events such as cache line
	28	* line fills so that we avoid infinite stalls later on as
	29	* much as possible. This code is in L1, so it won't trigger
	30	* any such event after this point in time.
	31	*/
	32	__builtin_bfin_ssync();
	33
9aeab10b MF	34	/* Initiate System software reset. */
9aeab10b MF	35	bfin_write_SWRST(0x7);
9171fc81	36
9aeab10b MF	37	/* Due to the way reset is handled in the hardware, we need
	38	* to delay for 10 SCLKS. The only reliable way to do this is
	39	* to calculate the CCLK/SCLK ratio and multiply 10. For now,
	40	* we'll assume worse case which is a 1:15 ratio.
	41	*/
	42	asm(
	43	"LSETUP (1f, 1f) LC0 = %0\n"
	44	"1: nop;"
	45	:
	46	: "a" (15 * 10)
	47	: "LC0", "LB0", "LT0"
	48	);
9171fc81	49
9aeab10b MF	50	/* Clear System software reset */
9aeab10b MF	51	bfin_write_SWRST(0);
9171fc81	52
9aeab10b	53	/* The BF526 ROM will crash during reset */
cf8f2efb	54	#if defined(__ADSPBF522__) \|\| defined(__ADSPBF524__) \|\| defined(__ADSPBF526__)
08a82a44 MF	55	/* Seems to be fixed with newer parts though ... */
	56	if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
	57	bfin_read_SWRST();
cf8f2efb MF	58	#endif
cf8f2efb MF	59
9aeab10b MF	60	/* Wait for the SWRST write to complete. Cannot rely on SSYNC
	61	* though as the System state is all reset now.
	62	*/
	63	asm(
	64	"LSETUP (1f, 1f) LC1 = %0\n"
	65	"1: nop;"
	66	:
	67	: "a" (15 * 1)
	68	: "LC1", "LB1", "LT1"
	69	);
a2979dcd	70	#endif
9171fc81	71
cf8f2efb	72	while (1)
a2979dcd SZ	73	#if defined(__ADSPBF60x__)
	74	bfin_write_RCU0_CTL(0x1);
	75	#else
9171fc81 MF	76	/* Issue core reset */
9171fc81 MF	77	asm("raise 1");
a2979dcd	78	#endif
9171fc81 MF	79	}
	80
	81	/* We need to trampoline ourselves up into L1 since our linker
	82	* does not have relaxtion support and will only generate a
	83	* PC relative call with a 25 bit immediate. This is not enough
	84	* to get us from the top of SDRAM into L1.
	85	*/
eed1a7b1	86	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
9171fc81 MF	87	{
	88	if (board_reset)
	89	board_reset();
9aeab10b MF	90	if (ANOMALY_05000353 \|\| ANOMALY_05000386)
	91	while (1)
	92	asm("jump (%0);" : : "a" (bfin_reset));
	93	else
	94	bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
9171fc81 MF	95	return 0;
9171fc81 MF	96	}