[people/ms/u-boot.git] / arch / blackfin / include / asm / mach-bf518 / anomaly.h

/*
 * DO NOT EDIT THIS FILE
 * This file is under version control at
 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
 * and can be replaced with that version at any time
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
 * Licensed under the ADI BSD license.
 *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */

/* This file should be up to date with:
 *  - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
 */

#if __SILICON_REVISION__ < 0
# error will not work on BF518 silicon version
#endif

#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_

/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
#define ANOMALY_05000421 (1)
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
#define ANOMALY_05000422 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Incorrect L1 Instruction Bank B Memory Map Location */
#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* PWM_TRIPB Signal Not Available on PG10 */
#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
/* SPI Master Boot Can Fail Under Certain Conditions */
#define ANOMALY_05000490 (1)
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
#define ANOMALY_05000494 (1)
/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
#define ANOMALY_05000498 (1)
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
#define ANOMALY_05000501 (1)

/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (0)
#define ANOMALY_05000357 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000480 (0)

#endif
Commit	Line	Data
2c0a6f2d MF	1	/*
	2	* DO NOT EDIT THIS FILE
	3	* This file is under version control at
	4	* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
	5	* and can be replaced with that version at any time
	6	* DO NOT EDIT THIS FILE
	7	*
bc9c6427	8	* Copyright 2004-2011 Analog Devices Inc.
2c0a6f2d MF	9	* Licensed under the ADI BSD license.
	10	* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
	11	*/
	12
	13	/* This file should be up to date with:
bc9c6427	14	* - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
2c0a6f2d MF	15	*/
2c0a6f2d MF	16
2c0a6f2d MF	17	#if __SILICON_REVISION__ < 0
	18	# error will not work on BF518 silicon version
	19	#endif
	20
	21	#ifndef _MACH_ANOMALY_H_
	22	#define _MACH_ANOMALY_H_
	23
	24	/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
	25	#define ANOMALY_05000074 (1)
	26	/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
	27	#define ANOMALY_05000119 (1)
	28	/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
	29	#define ANOMALY_05000122 (1)
	30	/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
	31	#define ANOMALY_05000245 (1)
	32	/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
	33	#define ANOMALY_05000254 (1)
	34	/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
	35	#define ANOMALY_05000265 (1)
	36	/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
	37	#define ANOMALY_05000310 (1)
	38	/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
	39	#define ANOMALY_05000366 (1)
	40	/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
	41	#define ANOMALY_05000405 (1)
	42	/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
	43	#define ANOMALY_05000408 (1)
	44	/* Speculative Fetches Can Cause Undesired External FIFO Operations */
	45	#define ANOMALY_05000416 (1)
	46	/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
	47	#define ANOMALY_05000421 (1)
	48	/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
	49	#define ANOMALY_05000422 (1)
	50	/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
	51	#define ANOMALY_05000426 (1)
	52	/* Software System Reset Corrupts PLL_LOCKCNT Register */
	53	#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
	54	/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
	55	#define ANOMALY_05000431 (1)
	56	/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
	57	#define ANOMALY_05000434 (1)
	58	/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
	59	#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
	60	/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
	61	#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
	62	/* Preboot Cannot be Used to Alter the PLL_DIV Register */
	63	#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
	64	/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
	65	#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
	66	/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
	67	#define ANOMALY_05000443 (1)
	68	/* Incorrect L1 Instruction Bank B Memory Map Location */
	69	#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
	70	/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
	71	#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
	72	/* PWM_TRIPB Signal Not Available on PG10 */
	73	#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
	74	/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
	75	#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
	76	/* False Hardware Error when RETI Points to Invalid Memory */
	77	#define ANOMALY_05000461 (1)
	78	/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
bc9c6427	79	#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
2c0a6f2d	80	/* Incorrect Default MSEL Value in PLL_CTL */
bc9c6427	81	#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
2c0a6f2d MF	82	/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
	83	#define ANOMALY_05000473 (1)
	84	/* TESTSET Instruction Cannot Be Interrupted */
	85	#define ANOMALY_05000477 (1)
	86	/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
	87	#define ANOMALY_05000481 (1)
bc9c6427 MF	88	/* PLL Latches Incorrect Settings During Reset */
	89	#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
	90	/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
	91	#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
	92	/* SPI Master Boot Can Fail Under Certain Conditions */
	93	#define ANOMALY_05000490 (1)
	94	/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
e5d8984b	95	#define ANOMALY_05000491 (1)
bc9c6427 MF	96	/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
	97	#define ANOMALY_05000494 (1)
	98	/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
	99	#define ANOMALY_05000498 (1)
	100	/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
	101	#define ANOMALY_05000501 (1)
2c0a6f2d MF	102
	103	/* Anomalies that don't exist on this proc */
	104	#define ANOMALY_05000099 (0)
	105	#define ANOMALY_05000120 (0)
	106	#define ANOMALY_05000125 (0)
	107	#define ANOMALY_05000149 (0)
	108	#define ANOMALY_05000158 (0)
	109	#define ANOMALY_05000171 (0)
	110	#define ANOMALY_05000179 (0)
	111	#define ANOMALY_05000182 (0)
	112	#define ANOMALY_05000183 (0)
	113	#define ANOMALY_05000189 (0)
	114	#define ANOMALY_05000198 (0)
	115	#define ANOMALY_05000202 (0)
	116	#define ANOMALY_05000215 (0)
	117	#define ANOMALY_05000219 (0)
	118	#define ANOMALY_05000220 (0)
	119	#define ANOMALY_05000227 (0)
	120	#define ANOMALY_05000230 (0)
	121	#define ANOMALY_05000231 (0)
	122	#define ANOMALY_05000233 (0)
	123	#define ANOMALY_05000234 (0)
	124	#define ANOMALY_05000242 (0)
	125	#define ANOMALY_05000244 (0)
	126	#define ANOMALY_05000248 (0)
	127	#define ANOMALY_05000250 (0)
	128	#define ANOMALY_05000257 (0)
	129	#define ANOMALY_05000261 (0)
	130	#define ANOMALY_05000263 (0)
	131	#define ANOMALY_05000266 (0)
	132	#define ANOMALY_05000273 (0)
	133	#define ANOMALY_05000274 (0)
	134	#define ANOMALY_05000278 (0)
	135	#define ANOMALY_05000281 (0)
	136	#define ANOMALY_05000283 (0)
	137	#define ANOMALY_05000285 (0)
	138	#define ANOMALY_05000287 (0)
	139	#define ANOMALY_05000301 (0)
	140	#define ANOMALY_05000305 (0)
	141	#define ANOMALY_05000307 (0)
	142	#define ANOMALY_05000311 (0)
	143	#define ANOMALY_05000312 (0)
	144	#define ANOMALY_05000315 (0)
	145	#define ANOMALY_05000323 (0)
	146	#define ANOMALY_05000353 (0)
	147	#define ANOMALY_05000357 (0)
	148	#define ANOMALY_05000362 (1)
	149	#define ANOMALY_05000363 (0)
	150	#define ANOMALY_05000364 (0)
	151	#define ANOMALY_05000371 (0)
	152	#define ANOMALY_05000380 (0)
bc9c6427	153	#define ANOMALY_05000383 (0)
2c0a6f2d MF	154	#define ANOMALY_05000386 (0)
	155	#define ANOMALY_05000389 (0)
	156	#define ANOMALY_05000400 (0)
	157	#define ANOMALY_05000402 (0)
	158	#define ANOMALY_05000412 (0)
	159	#define ANOMALY_05000432 (0)
	160	#define ANOMALY_05000447 (0)
	161	#define ANOMALY_05000448 (0)
	162	#define ANOMALY_05000456 (0)
	163	#define ANOMALY_05000450 (0)
	164	#define ANOMALY_05000465 (0)
	165	#define ANOMALY_05000467 (0)
	166	#define ANOMALY_05000474 (0)
	167	#define ANOMALY_05000475 (0)
bc9c6427	168	#define ANOMALY_05000480 (0)
2c0a6f2d MF	169
2c0a6f2d MF	170	#endif